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Type of parallel processing
Single instruction, multiple data (SIMD) is a type of parallel computing (processing) in Flynn's taxonomy. SIMD describes computers with multiple processing
Single instruction, multiple data
Single_instruction,_multiple_data
Parallel computing execution model
Single instruction, multiple threads (SIMT) is an execution model used in parallel computing where a single central "control unit" broadcasts an instruction
Single instruction, multiple threads
Single_instruction,_multiple_threads
Computing technique employed to achieve parallelism
In computing, multiple instruction, multiple data (MIMD) is a technique employed to achieve parallelism. Machines using MIMD have a number of processor
Multiple instruction, multiple data
Multiple_instruction,_multiple_data
Parallel computing architecture
In computing, multiple instruction, single data (MISD) is a type of parallel computing architecture where many functional units perform different operations
Multiple instruction, single data
Multiple_instruction,_single_data
Class of computer architecture
single instruction stream, single data stream (SISD) is a computer architecture in which a single uni-core processor executes a single instruction stream
Single instruction, single data
Single_instruction,_single_data
Computing technique used to achieve parallelism
computing, single program, multiple data (SPMD) is a term that has been used to refer to computational models for exploiting parallelism whereby multiple processors
Single_program,_multiple_data
The x86 instruction set has several times been extended with SIMD (Single instruction, multiple data) instruction set extensions. These extensions, starting
List_of_x86_SIMD_instructions
Computer processor which works on arrays of several numbers at once
accelerators but these are invariably Single instruction, multiple threads (SIMT) and occasionally Single instruction, multiple data (SIMD). Vector machines appeared
Vector_processor
Parallel processing technique
performing parallel operations on data contained in a processor register. SIMD stands for single instruction, multiple data. Many modern general-purpose computer
SWAR
Instruction set designed by Intel
MMX is a single instruction, multiple data (SIMD) instruction set architecture extension* designed by Intel, introduced on January 8, 1997 with its Pentium
MMX_(instruction_set)
Use of two or more central processing units (CPUs) within one computer system
execute a single sequence of instructions in multiple contexts (single instruction, multiple data (SIMD), often used in vector processing), multiple sequences
Multiprocessing
Extension to the x86 instruction set by AMD
instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set
3DNow!
Proprietary language for AI accelerators
effectively use certain types of CPU optimizations directly, like single instruction, multiple data (SIMD) with minor intervention by a developer, as occurs in
Mojo_(programming_language)
Model that describes the programmable interface of a computer processor
four instructions. 3-operand, allowing better reuse of data: CISC — It becomes either a single instruction: add a,b,c C = A+B needs one instruction. CISC
Instruction_set_architecture
Intel SIMD processor supplementary instruction sets introduced by Intel
Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets introduced by Intel with the initial
SSE2
Computer chip instruction set extension
computing, Streaming SIMD Extensions (SSE) is a single instruction, multiple data (SIMD) instruction set extension to the x86 architecture, designed by
Streaming_SIMD_Extensions
long instruction word (VLIW, Multiple Instruction Multiple Data (MIMD), up to 256 bit) instruction set it additionally uses a 4-way single instruction, multiple
FR-V_(microprocessor)
Central computer component that executes instructions
every instruction. Using Flynn's taxonomy, these two schemes of dealing with data are generally referred to as single instruction stream, multiple data stream
Central_processing_unit
Specialized computer hardware
architectures Single instruction, multiple data (SIMD) Single instruction, multiple threads (SIMT) Multiple instructions, multiple data (MIMD) High-level
Hardware_acceleration
royalty-free APIs help developers take advantage of single instruction, multiple data (SIMD) instructions. The library supports Intel and compatible processors
Integrated Performance Primitives
Integrated_Performance_Primitives
Topics referred to by the same term
may refer to: 2010, in Roman numerals MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel MMX Mineração, a Brazilian
MMX
Computer architecture to aid parallelism
processor chip design company Single instruction, multiple data – Type of parallel processing Single instruction, multiple threads – Parallel computing
Very_long_instruction_word
AMD computing architecture
architecture of a single AI engine integrates vector processors and scalar processors to implement Single Instruction Multiple Data (SIMD) capabilities
AI_engine
Class of computer processors
processor where a single instruction operates simultaneously on multiple data items (and thus is referred to as a single instruction, multiple data (SIMD) processor)
Scalar_processor
Supercomputer designed by Tesla
resources. The D1 instruction set supports both 64-bit scalar and 64-byte single instruction, multiple data (SIMD) vector instructions. The integer unit
Tesla_Dojo
processor which uses content-addressable memory. STARAN is a single instruction, multiple data array processor with a 4x256 1-bit processing element (PE)
STARAN
Microprocessor developed by Hewlett-Packard
multimedia instructions, an early single instruction, multiple data (SIMD) multimedia instruction set extension that provided instructions for improving
PA-7100LC
Quickly accessible working storage available as part of a digital processor
or pi. Vector registers hold data for vector processing done by SIMD instructions (Single Instruction, Multiple Data). Status registers hold truth values
Processor_register
Revision of the C++ programming language released in 2026
reclamation read-copy-update mechanism <simd>: Data-parallel access (Single instruction, multiple data or SIMD) support <text_encoding>: Support for accessing
C++26
Topics referred to by the same term
Christmas" Blitzen (computer), an SIMD (single instruction, multiple data) computer system Blitzen, a superhero from multiple Milestone Media comic books Blitzen
Blitzen
Family of RISC-based computer architectures
instructions, but these operated on each vector element sequentially and thus did not offer the performance of true single instruction, multiple data
Arm_architecture_family
Supercomputer
perform the same operation on multiple data points simultaneously, i.e., to execute tasks in single instruction, multiple data (SIMD) fashion. The CM-1, depending
Connection_Machine
Neural network based evaluation function
incremental computation and single instruction multiple data (SIMD) techniques along with appropriate intrinsic instructions. In contrast, deep neural network-based
Efficiently updatable neural network
Efficiently_updatable_neural_network
Programming paradigm in which many processes are executed simultaneously
The single-instruction-single-data (SISD) classification is equivalent to an entirely sequential program. The single-instruction-multiple-data (SIMD) classification
Parallel_computing
Programming language
originally a single instruction, single data (SISD) engine, but single instruction, multiple data (SIMD) and multiple instruction, multiple data (MIMD) functionality
SAS_language
Classification of computer architectures
had multiple cores) and older mainframe computers. A single instruction is simultaneously applied to multiple different data streams. Instructions can
Flynn's_taxonomy
Topics referred to by the same term
(computing), aka a data pipeline, a set of data processing elements connected in series Protocol pipelining, a technique in which multiple requests are written
Pipelining
64-bit RISC instruction set architecture
Motion Video Instructions (MVI) was an instruction set extension to the Alpha ISA that added instructions for single instruction, multiple data (SIMD) operations
DEC_Alpha
Specialized electronic circuit that accelerates graphics
running the single active program simultaneously on many example problems in parallel, using the GPU's single instruction, multiple data (SIMD) architecture
Graphics_processing_unit
Open standard for parallelizing
computations to devices like GPUs or FPGAs. It also added SIMD (Single Instruction, Multiple Data) directives for vectorization and user-defined reductions
OpenMP
Micro-electronic component
single instruction, multiple data (SIMD) instruction set architectures, and are therefore highly amenable to exploiting instruction-level parallelism through
System_on_a_chip
Massively parallel processing computer
operated in a single instruction, multiple data (SIMD) fashion—each PE performed the same operation simultaneously, on different data elements, under
Goodyear_MPP
Computer instruction set architecture
floating-point instructions. There are provisions for single instruction, multiple data (SIMD) operations on integer and floating-point data on up to 16
Power_ISA
Central processing unit by Sony Computer Entertainment and Toshiba
single instruction, multiple data (SIMD) fashion (e.g. four 32-bit integers could be added to four others using a single instruction). Instructions defined
Emotion_Engine
CPU that implements instruction-level parallelism within a single processor
processor (or multiple-issue processor) is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In
Superscalar_processor
Open-source CPU instruction set architecture
use the floating-point registers' bits to perform parallel single instruction, multiple data (SIMD) sub-word arithmetic. In 2017 a vendor published a more
RISC-V
Computer architecture bit width
floating-point arithmetic. Most modern CPUs feature single instruction, multiple data (SIMD) instruction sets (Streaming SIMD Extensions, AltiVec etc.) where
128-bit_computing
SIGGRAPH—Special Interest Group on Graphics SIMD—Single instruction, multiple data SIM—Subscriber Identity Module SIMM—Single inline memory module SIP—Session Initiation
List of computing and IT abbreviations
List_of_computing_and_IT_abbreviations
Function whose implementation is handled specially by the compiler
implement intrinsics that map directly to the x86 single instruction, multiple data (SIMD) instructions (MMX, Streaming SIMD Extensions (SSE), SSE2, SSE3
Intrinsic_function
Instructions a computer can execute
memory and interface with functions. Single instruction, multiple data (SIMD) instructions to increase speed when multiple processors are available to perform
Computer_program
Intel microprocessor
Pentium MMX also added the MMX instruction set, a basic integer single instruction, multiple data (SIMD) instruction set extension marketed for use in
Pentium_(original)
Family of digital signal processor microprocessors
multithreading, privilege levels, very long instruction word (VLIW), single instruction, multiple data (SIMD), and instructions geared toward efficient signal processing
Qualcomm_Hexagon
American supercomputer and AI firm (1983–1994)
into the parallel instruction set of the Connection Machine. The CM-1 through CM-200 were examples of single instruction, multiple data (SIMD) architecture
Thinking_Machines_Corporation
Increasing execution speed and reducing the overheads associated with loops
loop-sectioning is a loop-transformation technique for enabling SIMD (single instruction, multiple data)-encodings of loops and improving memory performance. This
Loop_optimization
Ability of computer instructions to be executed simultaneously with correct results
average number of instructions run per step of this parallel execution. ILP must not be confused with concurrency. In ILP, there is a single specific thread
Instruction-level_parallelism
Ability of a CPU to provide multiple threads of execution concurrently
ability of a central processing unit (CPU) (or a single core in a multi-core processor) to provide multiple threads of execution. The multithreading paradigm
Multithreading (computer architecture)
Multithreading_(computer_architecture)
Assembly language and bytecode for web browsers
adds many single instruction, multiple data (SIMD) related instructions and a new v128 datatype, with the ability for functions to return multiple values
WebAssembly
Functional programming language for arrays
traditional arithmetic and algebraic notation. Having single character names for single instruction, multiple data (SIMD) vector functions is one way that APL enables
APL_(programming_language)
Form of parallel computing
cycle. DDR2 SDRAM transfers a minimum of 256 bits per burst. Single Instruction, Multiple Data (SIMD) SIMD Within A Register David E. Culler, Jaswinder Pal
Bit-level_parallelism
addressing of units of data (such as bytes) that are smaller than some of the data formats. In some architectures, an instruction has a single opcode. In others
Comparison of instruction set architectures
Comparison_of_instruction_set_architectures
Type of computer instruction set
instruction includes the address of the data. One-address machines have the disadvantage that even simple actions like an addition require multiple instructions
Orthogonal_instruction_set
Declarative logic programming language
shared-memory setting may be further divided into single instruction, multiple data and multiple instruction, multiple data paradigms: Datalog engines that execute
Datalog
Microcode in x86 Intel processors
modified to convert the new MMX instructions to Pentium Pro processor-specific uops (new Single Instruction Multiple Data [SIMD] uops were added to implement
Intel_microcode
Low-power mobile multimedia processor
subsystems, the most abundant being the QPUs. A QPU is a 16-way single instruction, multiple data (SIMD) processor. "Each processor has two vector floating-point
VideoCore
List of x86 microprocessor instructions
The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support. The instructions are usually part of an executable
List_of_x86_instructions
Errors in computer data that introduce unintended changes to the original data
evaluate parity bits for data across a set of hard disks and can reconstruct corrupted data upon the failure of a single or multiple disks, depending on the
Data_corruption
Abstract machine that uses only one instruction
that uses only one instruction – obviating the need for a machine language opcode. With a judicious choice for the single instruction and given arbitrarily
One-instruction_set_computer
Mainframe computer, 1960s
power-on time it is in multiple tag mode, compatible with the 709 and 7090, and requires a Leave Multiple Tag Mode instruction in order to enter seven
IBM_7090
Topics referred to by the same term
Institute of Management and Technology Single instruction, multiple threads, relates to single instruction, multiple data (SIMD) Saigon Institute of Management
SIMT
Hardware cache of a central processing unit
have a hierarchy of multiple cache levels (L1, L2, often L3, and rarely even L4), with separate instruction-specific (I-cache) and data-specific (D-cache)
CPU_cache
TypeScript-based programming language
WebAssembly instructions that mirror instructions available on modern processors such as single instruction, multiple data (SIMD) and vector instructions and
AssemblyScript
Computing system
GPUs are very well suited to perform single instruction, multiple data (SIMD) and single instruction, multiple threads (SIMT), while modern CPUs are
Heterogeneous System Architecture
Heterogeneous_System_Architecture
Base memory unit handled by a computer
fixed-sized datum handled as the natural or historical unit of data by the instruction set or the hardware of a processor. The number of bits or digits
Word_(computer_architecture)
Microprocessor development project
and instructions for synchronizing and interrupt handling between multiple processors. Another notable feature is a rich set of single instruction, multiple
OpenRISC
4-component vector data type in computer science
4D vectors with instructions dealing with 4 lane single instruction, multiple data (SIMD) instructions, usually with a 128-bit data path and 32-bit floating
4D_vector
Algorithm for determining similar regions between two molecular sequences
implementation of the Smith–Waterman algorithm using the single instruction, multiple data (SIMD) technology available in Intel Pentium MMX processors
Smith–Waterman_algorithm
Virtual machine software
application. To enable mixing of code from any programming language in a single application, billed as a "polyglot application." GraalVM has its roots in
GraalVM
Component of computer engineering
programs, all single- or multi-chip CPUs: Read an instruction and decode it Find any associated data that is needed to process the instruction Process the
Microarchitecture
Instructions directly executable by a computer
which must run on multiple instruction-set-incompatible processor platforms. This property is also used to find unintended instructions called gadgets in
Machine_code
Computer architecture bit width
64-bit data bus, for instance). Processor registers are typically divided into several groups: integer, floating-point, single instruction, multiple data (SIMD)
64-bit_computing
Instruction set extension by Intel
implementations. Besides widening most 256-bit instructions, the extensions introduce various new operations, such as new data conversions, scatter operations, and
AVX-512
Processors using some version of the MIPS architecture
announced in 1985. It added multiple-cycle multiply and divide instructions in a somewhat independent on-chip unit. New instructions were added to retrieve
MIPS_architecture_processors
Collection of classes and functions used in the C++ programming language
std and std.compat" (PDF). open-std.org. WG21.{{cite web}}: CS1 maint: multiple names: authors list (link) "Apache C++ Standard Library". Archived from
C++_Standard_Library
Data processing chain
(CPUs) and other microprocessors to allow overlapping execution of multiple instructions with the same circuitry. The circuitry is usually divided up into
Pipeline_(computing)
Computer synchronizing instruction
barrier, also known as a membar, memory fence or fence instruction, is a type of barrier instruction that causes a central processing unit (CPU) or compiler
Memory_barrier
Processor executing one instruction in minimal clock cycles
architecture in which the instructions that perform arithmetic and tests operate only on the registers, and the instructions that access data in the main memory
Reduced instruction set computer
Reduced_instruction_set_computer
Algorithm that combines multiple sorted lists into one
sorting circuits, as well as in modern processors with single-instruction multiple-data (SIMD) instructions. Existing parallel algorithms are based on modifications
Merge_algorithm
Microprocessor series by AMD
instruction set developed by Advanced Micro Devices (AMD). It added single instruction multiple data (SIMD) instructions to the base x86 instruction set
AMD_K6-III
Nikon media processors
up to 28 instructions per clock cycle and core. Due to the used four-way single instruction, multiple data (SIMD) vector processor units, data is processed
Expeed
SIMD Computer System
Blitzen was a miniaturized SIMD (single instruction, multiple data) computer system designed for NASA in the late 1980s by a team of researchers at Duke
Blitzen_(computer)
Way in which data is arranged and accessed in computer memory
that the data's memory address is a multiple of the data size. For instance, in a 32-bit architecture, the data may be aligned if the data is stored
Data_structure_alignment
Microprocessor designed by Fujitsu
executes Visual Instruction Set (VIS) instructions, a set of single instruction, multiple data (SIMD) instructions. All instructions are pipelined except
SPARC64_V
RISC microprocessor
executing Motion Video Instructions (MVI), an extension to the Alpha Architecture defining single instruction multiple data (SIMD) instructions for multimedia
Alpha_21264
SQL relational database management system
cache-fitting vectors of data. This allows to involve the principles of vector processing and single instruction, multiple data (SIMD)— to perform the same
Actian_Vector
Method of constructing a computer processor
CPU to implement multiple parallel simple virtual machines using general logic instructions to perform single-instruction multiple-data (SIMD) operations
Bit_slicing
Computer architecture where code and data each have a separate bus
signal pathways for instructions and data. It is often contrasted with the von Neumann architecture, where program instructions and data share the same memory
Harvard_architecture
Specialized microprocessor optimized for digital signal processing
often use special memory architectures that are able to fetch multiple data or instructions at the same time. Digital signal processing (DSP) algorithms
Digital_signal_processor
Fault-tolerant computer system
SIMT (Single instruction, multiple threads) architecture, lockstep execution ensures that all threads in a warp execute the same kernel instruction at the
Lockstep_(computing)
Computer architecture hardware algorithm
algorithm for dynamic scheduling of instructions that allows out-of-order execution and enables more efficient use of multiple execution units. It was developed
Tomasulo's_algorithm
Microprocessor
Motion Video Instructions (MVI), an extension to the Alpha Architecture which introduced single instruction multiple data (SIMD) instructions for improving
Alpha_21164
SINGLE INSTRUCTION-MULTIPLE-DATA
SINGLE INSTRUCTION-MULTIPLE-DATA
Surname or Lastname
English
English : metonymic occupational name for a maker of nails or pins, or nickname for a small, thin man, from Middle English tingle, a kind of very small nail (of North German origin).
Boy/Male
Muslim
Instruction
Surname or Lastname
English
English : habitational name from a place in Northamptonshire named Dingley, possibly from Middle English dingle ‘hollow’ + Old English lēah ‘woodland clearing’.
Boy/Male
Hindu, Indian, Tamil
Multiple
Boy/Male
Indian
Instruction
Boy/Male
Muslim/Islamic
Instruction
Boy/Male
Arabic, Muslim
Education; Instruction
Surname or Lastname
English (West Midlands)
English (West Midlands) : occupational name for a worker in the linen or hemp industry, from an agent derivative of Middle English swingle ‘swingle’ (see Swingle).
Surname or Lastname
English
English : from Middle English sengler, syngler ‘singular’ (Old French se(i)ngler), perhaps a nickname for a solitary person.German : topographic name for a valley dweller, from a diminutive of Middle High German senke ‘valley’ + the suffix -er, denoting an inhabitant.German : habitational name for someone from Singeln near Waldshut.German : variant of Sing 1.
Surname or Lastname
English
English : topographic name for someone who lived in a place cleared of woods by fire, from Middle English sengle ‘burnt clearing’.German : from a pet form of a short form of a Germanic person name formed with sing ‘sing’ as the first element.
Surname or Lastname
English
English : metonymic occupational name for a worker in the linen or hemp industry, from Middle English swingle ‘swingle’, a wooden implement used for beating flax or hemp (Middle Dutch swinghel, from the verb ‘to swing’).Possibly an Americanized spelling of German Zwingel, a topographic name from Middle High German zwingel ‘citadel’.
Boy/Male
Australian, Vietnamese
Many; Multiple
Surname or Lastname
English
English : occupational name from an agent derivative of Middle English tingle (see Tingle).German : occupational or status name for a medieval judge or court official, from Old High German ding ‘legal proceeding’.German : variant of Tengler.
Surname or Lastname
English
English : topographic name for someone living in a small wooded dell or hollow, Middle English dingle (of uncertain origin). There is a district of Liverpool called Dingle.South German : nickname or status name for a smallholder, from Middle High German dingelīn ‘smallholding’.Americanized spelling of the old Prussian name Dingel or Dyngele, possibly from Germanic thing ‘legal assembly’.
Surname or Lastname
English
English : variant of Ingle.
Surname or Lastname
English
English : from the Old English personal name Hringwulf.German : from a short form of a Germanic personal name based on hring ‘ring’.German : metonymic occupational name for a ring maker (see Ringler).German : altered spelling of Ringel, an Old Prussian personal name.
Surname or Lastname
English
English : from either of two Old Norse personal names: Ingjaldr, in which the prefix in- probably reinforces the element -gjaldr, related to Old Norse gjalda ‘to pay or recompense’, or Ingólfr ‘Ing’s wolf’ (Ing was an ancient Germanic fertility god).English : habitational name from Ingol in Lancashire, which is named from the Old English personal name Inga + holh ‘hollow’, ‘depression’.Probably a variant of German Ingel, from a short form of any of several Germanic personal names formed with Ing- (see 1 above).An early bearer, Richard Ingle (1609–c. 1653), was a rebel and a pirate who first came to the colonies in 1631 or 1632 as a tobacco merchant. He is known to have practiced piracy in MD.
Male
Norwegian
Norwegian form of Old Norse Sindri, possibly SINDRE means "sparkling."
Surname or Lastname
English
English : occupational name for someone who laid wooden tiles (shingles) on roofs, from an agent derivative of Middle English schingle ‘shingle’.
Surname or Lastname
English
English : perhaps a metonymic occupational name for a spindle maker, from Middle English spindle, spindel (Old English spinel).Americanized spelling of German and Jewish Spindel.
SINGLE INSTRUCTION-MULTIPLE-DATA
SINGLE INSTRUCTION-MULTIPLE-DATA
Girl/Female
Bengali, Gujarati, Hindu, Indian
Beauty; Beautiful
Surname or Lastname
German
German : unexplained. It may be an altered form of a French Huguenot name, possibly Bassin.English and Scottish : patronymic from Bate.
Girl/Female
Arabic, Muslim
Fame; Nobility; Intelligence; Brightness; Brilliance
Boy/Male
Irish
Brave.
Surname or Lastname
English
English : nickname for a cheerful person, from Middle English rote ‘glad’ (Old English rÅt).English : metonymic occupational name for a player on the rote, an early medieval stringed instrument (Middle English, Old French rote, of uncertain origin but apparently ultimately akin to Welsh crwth).Dutch : topographic name for someone who lived by a retting place (Dutch root, a derivative of ro(o)ten ‘to ret’, akin to modern English rot), a place where flax is soaked in tubs of water until the stems rot to release the linen fibers.
Boy/Male
Welsh English Shakespearean
Joy.
Boy/Male
Indian, Sanskrit
King of the Twice Born
Boy/Male
Indian
Lovely
Boy/Male
Tamil
Dharmishtha | தரà¯à®®à®¿à®·à¯à®Ÿà®¾
Lord of Dharma, Wants religion
Boy/Male
Slavic
Victorious; conquerer of the people.
SINGLE INSTRUCTION-MULTIPLE-DATA
SINGLE INSTRUCTION-MULTIPLE-DATA
SINGLE INSTRUCTION-MULTIPLE-DATA
SINGLE INSTRUCTION-MULTIPLE-DATA
SINGLE INSTRUCTION-MULTIPLE-DATA
a.
Not doubled, twisted together, or combined with others; as, a single thread; a single strand of a rope.
imp. & p. p.
of Single
a.
Hence, unmarried; as, a single man or woman.
a.
Manifold; multiple.
a.
Having many flues; as, a multiflue boiler. See Boiler.
a.
Pertaining to, or promoting, instruction; educational.
n. pl.
See Single, n., 2.
n.
One who, or that which, multiplies or increases number.
adv.
Without partners, companions, or associates; single-handed; as, to attack another singly.
a.
Conveying knowledge; serving to instruct or inform; as, experience furnishes very instructive lessons.
n. & v.
See Jingle.
v. t.
To add (any given number or quantity) to itself a certain number of times; to find the product of by multiplication; thus 7 multiplied by 8 produces the number 56; to multiply two numbers. See the Note under Multiplication.
n.
The act of instructing, teaching, or furnishing with knowledge; information.
a.
Having a single purpose; hence, artless; guileless; single-hearted.
a.
Simple; not wise; weak; silly.
imp. & p. p.
of Multiply
v. i.
To take the irrregular gait called single-foot;- said of a horse. See Single-foot.
v. t.
To cover with shingles; as, to shingle a roof.
n.
A unit; one; as, to score a single.
a.
Performed by one person, or one on each side; as, a single combat.