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CPU that implements instruction-level parallelism within a single processor
A superscalar processor (or multiple-issue processor) is a CPU that implements a form of parallelism called instruction-level parallelism within a single
Superscalar_processor
Class of computer processors
vector processors were first introduced. It was originally used to distinguish the older designs from the new vector processors. A superscalar processor (such
Scalar_processor
Central computer component that executes instructions
A central processing unit (CPU), also known as a central processor, main processor, or simply processor, is the primary processor in a given computer
Central_processing_unit
2012 computer chip design
like other ARM intellectual property and processor designs. 8-stage pipelined processor with 2-way superscalar, in-order execution pipeline DSP and NEON
ARM_Cortex-A53
Ability of a CPU to provide multiple threads of execution concurrently
advanced type of multithreading applies to superscalar processors. Whereas a normal superscalar processor issues multiple instructions from a single thread
Multithreading (computer architecture)
Multithreading_(computer_architecture)
Efficiency improving technique for superscalar CPUs
one cycle. The processor must be superscalar to do so. Chip-level multiprocessing (CMP or multicore): integrates two or more processors into one chip,
Simultaneous_multithreading
each other, and execute them in parallel. This approach is called superscalar processor design. Such methods are limited by the degree of instruction-level
History of general-purpose CPUs
History_of_general-purpose_CPUs
Programming paradigm in which many processes are executed simultaneously
multi-core processor is a processor that includes multiple processing units (called "cores") on the same chip. This processor differs from a superscalar processor
Parallel_computing
Classification of computer architectures
term for associative processor is analogous to cells of content-addressable memory each having their own processor. Such processors are very rare. broadcast_value
Flynn's_taxonomy
Software framework for heterogeneous computing systems
parallelism (ILP) Parallel computing Simultaneous multithreading Superscalar processor Symmetric multiprocessing (SMP) Variable SMP Thread (computing)
Simultaneous and heterogeneous multithreading
Simultaneous_and_heterogeneous_multithreading
Series of graphics processing units produced by ARM Holdings
Real, H.263. The Mali V52 video processor was released with the Mali G52 and G31 GPUs in March 2018. The processor is intended to support 4K (including
Mali_(processor)
Computing paradigm to improve computational efficiency
high-performance central processing units (CPUs) to make use of instruction cycles that would otherwise be wasted. In this paradigm, a processor executes instructions
Out-of-order_execution
CPU that switches between threads of execution on every cycle
automatically generate a corresponding barrel processor design from a single-tasking processor design. An n-way barrel processor generated this way acts much like
Barrel_processor
Average number of instructions executed for each clock cycle
keep doubling the speed of the clock, instruction pipelining and superscalar processor design have evolved so CPUs can use a variety of execution units
Instructions_per_cycle
Task of creating a processor
Processor design is a subfield of computer engineering and electronics that deals with creating a processor, a key component of computer hardware. While
Processor_design
Computer architecture to aid parallelism
which instructions execute in parallel. VLIW architectures contrast with superscalar architectures, the predominant approach for exploiting ILP, where hardware
Very_long_instruction_word
Problems with central processing unit design
3.2 Identication of Pipeline Hazards". Modern Processor Design: Fundamentals of Superscalar Processors. Waveland Press. pp. 73–78. ISBN 9781478610762
Hazard (computer architecture)
Hazard_(computer_architecture)
Microprocessor with more than one processing unit
A multi-core processor (MCP) is a microprocessor on a single integrated circuit (IC) with two or more separate central processing units (CPUs), called
Multi-core_processor
Superscalar efficiency technique
not to be confused with a multi-processor system. Most modern processors are superscalar. In a superscalar processor multiple instructions are dispatched
Shelving_buffer
CPU chip: 48. Manycore processors, originating from the cancelled Larrabee processor. 2010: Knights Ferry (32-core processor prototype on 45nm) 2012:
List_of_Intel_processors
Component of computer engineering
model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the instructions, execution model, processor registers
Microarchitecture
Specialized microprocessor optimized for digital signal processing
signal processor (DSP) is a specialized microprocessor chip, with its architecture optimized for the operational needs of digital signal processing. DSPs
Digital_signal_processor
Intel microprocessor
had also replaced the 486 brand. The P5 Pentium is the first superscalar x86 processor, meaning that it was often able to execute two instructions at
Pentium_(original)
CPU for the GameCube
Broadway processor, also designed and manufactured by IBM, that powers the Wii console. Customized PowerPC 750CXe core Clock rate – 486 MHz Superscalar Out-of-order
Gekko_(processor)
Mainframe computer by Control Data
worked on at the same time. Today,[timeframe?] this is known as a superscalar processor design, but it was unique for its time. Unlike most modern CPU designs
CDC_6600
CPU register containing flags
ISBN 978-0123747501. Shen, John; Lipasti, Mikko. Modern Processor Design: Fundamentals of Superscalar Processors. Waveland Press. ISBN 978-1478607830. "ARM Information
Status_register
Instruction pipeline
delay slot), so that they must insert NOPs into the delay slots. Superscalar processors, which fetch multiple instructions per cycle and must have some
Classic_RISC_pipeline
Instruction set
deprecated in 1998, when IBM introduced the POWER3 processor that was mainly a 32/64-bit PowerPC processor but included IBM POWER architecture features for
IBM_POWER_architecture
pipeline with 2-way decode, 3-way out-of-order speculatively issued superscalar execution Pipelined VFPv3 and 128-bit wide NEON (SIMD) 3 execution ports
Scorpion_(processor)
Frequency at which a CPU chip or core is operating
generator of a processor can generate pulses used to synchronize the operations of its components. It is used as an indicator of the processor speed. Clock
Clock_rate
Microarchitecture by Nvidia
in-order superscalar pipeline. Its design makes it suitable for integration with other SIPs cores (e.g. GPU, display controller, DSP, image processor, etc
Project_Denver
Family of PowerPC processors
Shen, John Paul; Lipasti, Mikko H. (2013). Modern processor design: fundamentals of superscalar processors (Reissued ed.). Long Grove, Illinois: Waveland
PowerPC_600
Computer component
or data hazard Scoreboarding Very long instruction word (VLIW) Superscalar processor Opcode Analysis of Instruction parallelism, Instruction frequencies
Instruction_unit
Experimental minicomputer by IBM
resulting in an experimental processor called "Cheetah". Cheetah was a 2-way superscalar processor, which evolved into a processor called "Panther" in 1985
IBM_801
the instruction window. Superscalar processor Shen and Lipasti. Modern Processor Design: Fundamentals of Superscalar Processors. McGraw-Hill, 2005. Patt
Instruction_window
Digital circuit
Shen, John P.; Lipasti, Mikko (2005). Modern processor design: fundamentals of superscalar processors. Boston: McGraw-Hill Higher Education. pp. 455
Branch_predictor
Computer architecture feature
In a single processor, MLP may be considered a form of instruction-level parallelism (ILP). However, ILP is often conflated with superscalar, the ability
Memory-level_parallelism
Multi-core processor with a large number of cores
Coherent Logix hx3100 Processor, a 100-core DSP/GPP processor based on HyperX Architecture Movidius Myriad 2, a manycore vision processing unit (VPU) Kalray
Manycore_processor
32-bit CPU for the Wii U
MESI/MERSI support Each core can output up to 4 instructions per clock using superscalar parallelism. 32-bit integer unit 64-bit floating-point unit (or 2 × 32-bit
Espresso_(processor)
Set of computers configured in a distributed computing system
massive parallelism. Unlike symmetric multi-processor systems, where scalability eventually fades as more processors are added (and thus either becomes more
Computer_cluster
Type of microprocessor developed in India
"Design and Implementation of a RISC-V ISA-based In-order Dual Issue Superscalar Processor" (PDF). RISC-V Summit. 5 December 2018. Retrieved 27 October 2021
VEGA_Microprocessors
Method of improving instruction-level parallelism
instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming
Instruction_pipelining
Message-passing system for parallel computers
rank-0 process, and some implementations also capture and funnel the output from other processes. MPI uses the notion of process rather than processor. Program
Message_Passing_Interface
Set of rules describing computer system
defines the machine code that a processor reads and acts upon as well as the word size, memory address modes, processor registers, and data type. Microarchitecture:
Computer_architecture
Processor with instructions capable of multi-step operations
modes than small 8-bit CISC processors. A PDP-10, a PDP-8, an x86 processor, an Intel 4004, a Motorola 68000-series processor, a IBM Z mainframe, a Burroughs
Complex instruction set computer
Complex_instruction_set_computer
Algorithm in numerical analysis
data dependency). This reduces the performance gain from modern superscalar processor designs. To reduce this penalty, one can split the accumulator variables
Kahan_summation_algorithm
Family of 64-bit Intel microprocessors
Itanium processor model had been designed to share a common chipset with the Intel Xeon processor EX (Intel's Xeon processor designed for four processor and
Itanium
Processor core in computers
32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. Compared to the ARM11, the Cortex-A8 is a dual-issue superscalar design
ARM_Cortex-A8
compression RISC processor IP core with a 6-stage pipeline; and later the first with a 7-stage pipeline dual-issue superscalar processor IP core coarse-grained
Lexra
Combinational digital circuit
depend on the architecture of the encapsulating processor and the operation being performed. Processor architectures vary widely, but in general-purpose
Arithmetic_logic_unit
32-bit CPU for the Wii
(ranging from 400 MHz–1000 MHz.) 90 nanometer process technology, shrunk to 65 nm in 2007. Superscalar Out-of-order execution PowerPC core, specially
Broadway_(processor)
Technique used in processor design
In computer science and processor design, speculative execution or speculation is a design characteristic where a processor is able to perform potentially
Speculative_execution
Microarchitecture designed by ARM Holdings
central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A57 is an out-of-order superscalar pipeline
ARM_Cortex-A57
Family of RISC microprocessors and microcontrollers
by a 4-entry TLB-like Physical Address Cache. Though it is not a superscalar processor, it permits a floating-point operation and an integer operation
AMD_Am29000
Operating system performance issue
of processors. Amdahl's law Lock (computer science) Lock-free programming Read-copy-update Concurrency control Serializability Superscalar processor Madnick
Software_lockout
Central processing unit
offer 90% greater performance. Pipelined processor with deeply out-of-order, speculative issue 3-way superscalar execution pipeline DSP and NEON SIMD extensions
ARM_Cortex-A72
Line of desktop and mobile microprocessors produced by Intel
The Pentium III (marketed as Intel Pentium III Processor, informally PIII or P3) brand refers to Intel's 32-bit x86 desktop and mobile CPUs based on the
Pentium_III
Concept in computer architecture and processor design
Pentium 4 processor and has continued to be a feature of their subsequent processors. Some variation of this system is may exist in other superscalar processors
Replay_system
Central processing unit by Sony Computer Entertainment and Toshiba
Synthesizer for rendering. The CPU core is a MIPS R5900 two-way superscalar in-order RISC processor based on the R5000, which implements the MIPS-III instruction
Emotion_Engine
Class of computer architecture
Michael J. Flynn, SISD can have concurrent processing characteristics. Pipelined processors and superscalar processors are common examples found in most modern
Single instruction, single data
Single_instruction,_single_data
Brand of discontinued microprocessors produced by Intel
original Pentium was Intel's fifth generation processor, succeeding the i486; Pentium was Intel's flagship processor line for over a decade until the introduction
Pentium
ARM microprocessor core model
Cambridge design centre. The Cortex-A55 is a two-wide decode in-order superscalar pipeline. The Cortex-A55 serves as the successor of the ARM Cortex-A53
ARM_Cortex-A55
Software library for numerical linear algebra
cache-based architectures and the instruction-level parallelism of modern superscalar processors, and thus can run orders of magnitude faster than LINPACK on such
LAPACK
RISC-based microprocessor design
(2003). Modern Processor Design: Fundamentals of Superscalar Processors (Beta ed.). McGraw Hill. p. 328. ISBN 0-07-282968-0. "i960 MX Processor". Military
Intel_i960
IBM midrange computer (1988–2013)
Shen; Mikko H. Lipasti (30 July 2013). Modern Processor Design: Fundamentals of Superscalar Processors. Waveland Press. ISBN 978-1-4786-1076-2. Adam T
IBM_AS/400
Nettop computer
an ARM v6/v7-compliant superscalar processor core, Vivante GC600 OpenGL 3.0 and OpenGL ES 2.0 capable 2D/3D graphics processing unit, Marvell vMeta HD
CuBox
Computer processor contained on an integrated-circuit chip
user interface, 16-, 32- or 64-bit processors are used. An 8- or 16-bit processor may be selected over a 32-bit processor for system on a chip or microcontroller
Microprocessor
2019 64-bit mainframe microprocessor by IBM
simultaneous multithreading. The cores implement the CISC z/Architecture with a superscalar, out-of-order pipeline. New in z15 is an on-chip nest accelerator unit
IBM_z15
Motorola 680x0 microprocessor, released in April 1994
Shen, John Paul; Lipasti, Mikko H. (2005). Modern Processor Design: Fundamentals of Superscalar Processors. McGraw-Hill. p. 423. ISBN 0-07-057064-7. Retrieved
Motorola_68060
Processor design concept
In computing and processor design, a translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory addresses
Translation_lookaside_buffer
American academic and engineer
"for important contributions to instruction level parallelism and superscalar processor design" 1999 IEEE Wallace W. McDowell Award "for your impact on
Yale_Patt
"ARM1136J(F)-S – ARM Processor". Arm.com. Archived from the original on 21 March 2009. Retrieved 18 April 2009. "ARM1156 Processor". Arm Holdings. Archived
List_of_ARM_processors
vector processor core. A 32-bit RISC instruction set in the superscalar core is combined with most variants integrating a dual 16-bit media processor also
FR-V_(microprocessor)
Proprietary simultaneous multithreading implementation by Intel
"physical" processor plus an extra "logical" processor to the host operating system (HTT-unaware operating systems see two "physical" processors), allowing
Hyper-threading
development of superscalar architecture rests. Pipeline burst cache can be found in DRAM controllers and chipset designs. In a processor-based system,
Pipeline_burst_cache
Part of a CPU which performs the operations instructed by the program
common for modern processing units to have multiple parallel functional units within its execution units, which is referred to as superscalar design. The simplest
Execution_unit
continuation of an application filed in 1992, later abandoned. Wider superscalar processors demand multiple instructions to be fetched in a single cycle for
Trace_cache
RISC instruction set architecture by AIM alliance
introduction of the PowerPC 970. The 970 is a 64-bit processor derived from the POWER4 server processor. To create it, the POWER4 core was modified to be
PowerPC
Part of a computer system
PDP-11/45 Processor Handbook (PDF). Digital Equipment Corporation. 1973. Chapter 7 "Floating Point Processor". Retrieved 2025-10-30. PDP-11 Processor Handbook
Floating-point_unit
Type of computer processor
computer processor that issues more than one instruction per clock cycle. They can be considered in three broad types: Statically-scheduled superscalar architectures
Wide-issue
32-bit RISC-like computing architecture
many processors of the time used either superscalar instruction dispatch or superpipelined operation, the Clipper C400 was the first processor to use
Clipper_architecture
Family of microprocessor cores with ARM microarchitecture
32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. It is a multicore processor with out-of-order superscalar pipeline
ARM_Cortex-A15
Series of pioneering microprocessors from the 1980s
instructions to different execution units. This is termed superscalar processing. Superscalar processors are suited for optimising the execution of sequentially
Transputer
Computer manufacturer and seller
performance was remarkable, since the processor would then initiate close to all 28 operations on average. Each 7/ processor datapath comprised a control unit
Multiflow
Network packet distribution with multiple cores
packets across the other cores of the processor. This comes at the cost of introducing additional inter-processor interrupts (IPIs); however the number
Multi-core network packet steering
Multi-core_network_packet_steering
Microarchitecture by AMD
module is equal to a dual-core processor in its integer calculation capabilities, and to either a single-core processor or a handicapped dual-core in terms
Bulldozer_(microarchitecture)
Intel-compatible processors HK386 and K486. Henry Wong — developed a 2-way superscalar, out-of-order execution, 32-bit x86 processor soft core running
List of former IA-32 compatible processor manufacturers
List_of_former_IA-32_compatible_processor_manufacturers
Hardware cache of a central processing unit
location in the memory, the processor checks whether the data from that location is already in the cache. If so, the processor will read from or write to
CPU_cache
Formal model in concurrency theory
superscalar pipelined processor designed to support large-scale multiprocessing. CSP was employed in verifying the correctness of both the processor pipeline
Communicating sequential processes
Communicating_sequential_processes
within standard computer processors, by writing code that allows the full use of existing parallel units within superscalar processors. "Cornell Virtual Workshop:
Microparallelism
Family of instruction set architectures
in 2005. Centaur's 2008 design, the VIA Nano, was their first processor with superscalar and speculative execution. It was introduced at about the same
X86
Ability of computer instructions to be executed simultaneously with correct results
the execution of multiple instructions can be partially overlapped. Superscalar execution, VLIW, and the closely related explicitly parallel instruction
Instruction-level_parallelism
Micro-electronic component
processor core by definition. The Arm architecture is a common choice for SoC processor cores because some Arm-architecture cores are soft processors
System_on_a_chip
Series of computer microprocessors developed by Jiāngnán Computing Lab
Peak memory bandwidth: 68 GB/s Quad-channel 128-bit DDR3 Four-issue superscalar Two integer and two floating-point execution units 7-stage integer pipeline
Sunway_(processor)
CPU optimization unit
for execution, increases the overall efficiency of the processor boosting its speed. The processor no longer has to wait for the memory access operations
Prefetch_input_queue
Microprocessor
and enhanced MAC units. v3: Added an optional MAC unit. v4: Limited superscalar core. v4e (or eV4 in some documents): Enhanced version of the v4, launched
NXP_ColdFire
Use of widely distributed computer resources to reach a common goal
contrast to the traditional notion of a supercomputer, which has many processors connected by a local high-speed computer bus. This technology has been
Grid_computing
Microprocessor microarchitecture
oriented processor may complete a single calculation significantly faster than a throughput-oriented processor; however, the throughput-oriented processor could
Latency oriented processor architecture
Latency_oriented_processor_architecture
Registers that count hardware-related activities
measurements to collect all desired performance metrics. Modern superscalar processors schedule and execute multiple instructions out-of-order at one time
Hardware_performance_counter
System-on-chip processors designed by Apple Inc.
includes a 64-bit ARMv8 processor (a variant of the processor in the A10 Fusion, or T8010) and a separate Secure Enclave Processor. It provides a secure
Apple_silicon
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