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Open-source CPU instruction set architecture
RISC-V (pronounced "risk-five") is a free and open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles
RISC-V
List of RISC-V microprocessor instructions
The RISC-V instruction set refers to the set of instructions that RISC-V compatible microprocessors support. The instructions are usually part of an executable
RISC-V_instruction_listings
Processor executing one instruction in minimal clock cycles
In electronics and computer science, a reduced instruction set computer (RISC, pronounced "risk") is a computer architecture designed to simplify the individual
Reduced instruction set computer
Reduced_instruction_set_computer
Assembly languages for the RISC-V computer architecture
RISC-V assembly language is a low-level programming language that is used to produce object code for the RISC-V class of processors. Assembly languages
RISC-V_assembly_language
Redmond is an American executive who was CEO of The RISC-V Foundation. Redmond joined the RISC-V Foundation in March 2019. Prior to her appointment, she
Calista_Redmond
The RISC-V ecosystem includes systems that boot with UEFI, handle power management with ACPI and run a variety of operating systems including Linux distributions
RISC-V_ecosystem
Computer architecture for security
Hardware Enhanced RISC Instructions (CHERI) is a technology designed to improve security for reduced instruction set computer (RISC) processors. CHERI
Capability Hardware Enhanced RISC Instructions
Capability_Hardware_Enhanced_RISC_Instructions
American fabless semiconductor design company
is most widely known for developing the MIPS architecture and a series of RISC CPU chips based on it. MIPS provides processor architectures and cores for
MIPS_Technologies
ARM- and RISC-V-architecture microcontroller by the Raspberry Pi Foundation
dual-core microcontroller (containing selectable ARM Cortex-M33 and/or Hazard3 RISC-V cores) by Raspberry Pi Ltd. In August 2024, it was released as part of the
RP2350
European legislative proposal
originally planned. The European Chips Act places a strategic emphasis on the RISC-V open-source instruction set architecture (ISA) as a mechanism to reduce
European_Chips_Act
Instruction set extensions accelerating AES operations
instructions were available on RISC-V, a number of RISC-V chips included integrated AES co-processors. Examples include: Dual-core RISC-V 64 bits Sipeed-M1 support
AES_instruction_set
British semiconductor and software design company
SoftBank Group. "ARM" was originally an acronym for Acorn RISC Machine and later for Advanced RISC Machines. While ARM CPUs first appeared in the Acorn Archimedes
Arm_Holdings
2019 Android mobile operating system
ported to the RISC-V architecture by Alibaba Group-owned T-Head. T-Head managed to get Android 10 running on a triple-core, 64-bit, RISC-V CPU of their
Android_10
Technology company based in Hong Kong
and sells RISC-V based hardware. Its flagship products are laptops, tablets and PC motherboards with various processors based on 64-bit RISC-V ISA. DeepComputing
DeepComputing
Operating modes for central processing unit
(B6500 series); there are multiple non-control modes in the B5000 series. RISC-V has three main CPU modes: User Mode (U), Supervisor Mode (S), and Machine
CPU_modes
Semiconductor manufacturing process
Wenzhong Bao and Peng Zhou announced that they had successfully created a 1nm RISC-V chip using two-dimensional semiconductors. "IRDS™ 2021: More Moore – IEEE
1_nm_process
Alibaba semiconductor subsidiary
Alibaba Group. T-Head focuses on open source instruction set architecture RISC-V in its processor design. In April 2018, Alibaba Group announced it would
T-Head
specialized in development of RISC-V based technologies. Currently located in Germany, the company aims to support and standardize RISC-V commercially. On August
Quintauris
Modern reimplementation of Sixth Edition Unix
reimplementation of Sixth Edition Unix in ANSI C for multiprocessor x86 and RISC-V systems. It was created for educational purposes in MIT's Operating System
Xv6
and field-programmable gate array (FPGA) Pinebook – Notebook from Pine64 RISC-V – an open-source hardware instruction set architecture SparkFun Electronics
List of open-source hardware projects
List_of_open-source_hardware_projects
Low-cost, low-power SoC microcontrollers with Bluetooth and Wi-Fi
dual-core and single-core variants, the Xtensa LX7 dual-core processor, or a RISC-V microprocessor. In addition, the ESP32 incorporates components essential
ESP32
Extensions to the x86 instruction set architecture
A SHA instruction set is a set of extensions to the ARM, RISC-V and x86 instruction set architecture which support hardware acceleration of the Secure
SHA_instruction_set
Smartwatch brand by Huami
EE Times reported that Huami claimed to have developed the world's first RISC-V-based AI-powered wearable chipset, the Huangshan-1 AI chip. In July 2018
Amazfit
American computer pioneer and academic (born 1947)
computer (RISC) design, having coined the term RISC, and by leading the Berkeley RISC project. As of 2018, 99% of all new chips use a RISC architecture
David Patterson (computer scientist)
David_Patterson_(computer_scientist)
American computer engineer
computer architecture. As of 2023[update], he is chairman of the Board of the RISC-V Foundation. Asanović was named Fellow of the Institute of Electrical and
Krste_Asanović
This article lists software emulators. ARMulator Aemulor QEMU SPIM: The OVPsim 500 mips MIPS32 emulator, can be used to develop software using virtual
List_of_emulators
Not-for-profit company headquartered in Cambridge, UK
develop and maintain open source silicon designs and tools. lowRISC is active in RISC-V-related open source hardware and software development and stewards
LowRISC
Fabless semiconductor company providing RISC-V processors
semiconductor IP company and provider of commercial RISC-V processors and silicon chips based on the RISC-V instruction set architecture (ISA). Its products
SiFive
Type of computer instructions
justifications, use-cases, c code, proofs and Verilog for each proposed RISC-V instruction. Particular practical examples include bit banging of GPIO using
Bit_manipulation_instructions
Modular handheld computer
configurations based on the Armv8-A architecture, and the R-01, based on RISC-V. The uConsole was created with the open-design philosophy. The case is available
UConsole
Chinese multinational technology company
its "AI champions" in 2018. On 27 July 2019, Alibaba unveiled a 64-bit RISC-V processor called the XuanTie-910 (Black Iron 910). It is a 12 nm 16-core
Alibaba_Group
Chinese Semiconductor Company
March 2022, it was reported that Espressif was moving exclusively to the RISC-V open source instruction set architecture. As of September 2023, Espressif
Espressif_Systems
target instruction sets, including ARM architecture, Atmel AVR, x86, x86-64, RISC-V, Freescale 68HC11, Freescale v4e, Motorola 680x0, MIPS, PowerPC, IBM System
Comparison_of_assemblers
Computer operating system
runs on 32-bit and 64-bit x86 processors, and recently has been ported to RISC-V; there is also a port for ARM under development, but is currently far behind
Haiku_(operating_system)
Garbage collection assisted by hardware mechanisms
additional memory lookups or bitmasking instructions. Research into the RISC-V ISA has led to the development of custom extensions like "Graceless," which
Hardware-assisted garbage collection
Hardware-assisted_garbage_collection
Computing chip company based in Hangzhou, China
2021, which is focused on computer processors based on the architecture RISC-V to be used mainly in the area of artificial intelligence (AI CPUs). In 2024
SpacemiT
Mechanism of function calls in computers
calling convention, often suggested by the architect. For RISCs including SPARC, MIPS, and RISC-V, registers names based on this calling convention are often
Calling_convention
16-bit computer number format
Intel® Builders Programs. Retrieved 13 May 2022. "RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA". Five EmbedDev. Retrieved 2023-07-02
Half-precision floating-point format
Half-precision_floating-point_format
Releases of Debian GNU/Linux, a computer operating system
"trixie" released". "RISC-V Debian wiki". "Phoronix: RISC-V Is Now An Official Debian Architecture". "Hackaday: Debian Officially Adds RISC-V Support". 25 July
Debian release version history
Debian_release_version_history
Free virtualization and emulation software
architecture on any other. QEMU supports the emulation of x86, ARM, PowerPC, RISC-V, and many others. QEMU is free software originally developed by Fabrice
QEMU
Rolling release Linux distribution
original on 11 January 2023. Retrieved 31 May 2022. "Arch Linux RISC-V". Arch Linux RISC-V. Archived from the original on 24 May 2022. Retrieved 31 May 2022
Arch_Linux
Way for programs to access kernel services
various levels; the code is an argument to the instruction. Within the RISC-V privileged architecture, the instruction ECALL (after environment call)
System_call
Swedish computer software company
market and, in more recent years, added 64-bit support to its Arm (2021) and RISC-V (2022) toolchains. IAR Systems is headquartered in Uppsala, Sweden, and
IAR_Systems
Netherlands-based chip company
the EuroHPC Joint Undertaking as part of the DARE (Digital Autonomy with RISC‑V for Europe) project to support the development of a high‑performance AI
Axelera_AI
Computer processor which works on arrays of several numbers at once
other reduction)". "Riscv-v-spec/V-spec.adoc at master · riscv/Riscv-v-spec". GitHub. 19 November 2022. Cray Overview RISC-V RVV ISA SX-Arora Overview
Vector_processor
CPU register that is always zero
set architectures including the CDC 6600, MIPS, SPARC, Alpha, ARM64, and RISC-V, among others. Zero appears as a constant in many instructions, notably
Zero_register
Free and open-source media player software
called mpv-android. It is cross-platform, running on ARM, MIPS, PowerPC, RISC-V, s390x, x86/IA-32, x86-64, and some other by 3rd party. mpv was forked by
Mpv_(media_player)
American computer company
Grimm (March 10, 2025). "RISC-V mini AI PC that fits inside a Framework laptop shell revealed — DeepComputing's DC-ROMA RISC-V AI PC claims 50 TOPS, 64GB
Framework_Computer
Standard file format for executables, object code, shared libraries, and core dumps
Executable Format) Haiku, an open source reimplementation of BeOS RISC OS Stratus VOS, in PA-RISC and x86 versions SkyOS Fuchsia OS Z/TPF HPE NonStop OS Deos
Executable and Linkable Format
Executable_and_Linkable_Format
Computer architecture bit width
console supported 128-bit addressing or 128-bit integer arithmetic. The RISC-V ISA specification from 2016 includes a reservation for a 128-bit version
128-bit_computing
Non-profit technology consortium to develop the Linux operating system
Trust Over IP Foundation (ToIP). The Linux Foundation Europe started the RISC-V Software Ecosystem (RISE) initiative on May 31, 2023. The goal of RISE is
Linux_Foundation
Series of Chinese single-board computers
computers, and video playback. The Orange Pi RV is a RISC-V capable SBC, aimed at development using RISC-V for a variety of applications such as complex image/video
Orange_Pi
Value for unrepresentable data
for Single-Precision Floating-Point, Version 2.2 / RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA". Five EmbedDev. Fog, Agner (11 April
NaN
Taiwanese semiconductor company
supplier of 32/64-bit embedded CPU cores and a founding Premier member of RISC-V International. It focuses on the embedded market and delivers CPU cores
Andes_Technology
Hobbyist desktop computing operating system
system. It features a preemptive kernel, currently supports x86-64, ARM, and RISC-V based computers, and hosts multiple complex applications including its own
SerenityOS
Real-time operating system
LPC1000 LPC2000 LPC4300 Renesas 78K0R RL78 H8/S RX600 RX200 SuperH V850 RISC-V RV32I RV64I PULP RI5CY Silicon Labs EFM32 Gecko (ARM Cortex) STMicroelectronics
FreeRTOS
Processor technology company
2015, Codasip co-founded RISC-V International (initially known as RISC-V Foundation) and also launched the first commercial RISC-V processor IP on the market
Codasip
Order of bytes in a computer word
ordering for processor architectures (x86, most ARM implementations, base RISC-V implementations) and their associated memory. File formats can use either
Endianness
Digital circuit
branch-prediction accuracy. The RISC-V ISA recommends that software written for RISC-V harts (hardware threads), or generated to run on RISC-V harts, be optimized
Branch_predictor
Computer vulnerability using speculative execution
talk "How Secure Are Commercial RISC-V CPUs?" covered the security properties of several commercially available RISC-V processors and showed that current
Transient execution CPU vulnerability
Transient_execution_CPU_vulnerability
Open source Linux distribution kit
IP32 (r5k & r10k) as the first Linux OS release to boot on multiple SGI RISC workstations and servers. In December 2024, version 24.12 was released with
T2_SDE
Set of real-time patches for Linux kernel
and enabled in mainline Linux on the supported architectures x86, x86_64, RISC-V and ARM64. This made kernel v6.12 the first release to include baked-in
PREEMPT_RT
German software company
committees and associated working groups over the past years: AUTOSAR, RISC-V, Nexus, ASAM, MIPI Debug Working Group, SPRINT Forum and Power.org. The
Lauterbach_(company)
(M0/3/4/7, A7/17/53, ARM9/11), x86, RISC-V HarmonyOS Proprietary closed embedded active AArch64, x86-64, RISC-V, LingxiISA IBM 4680 OS Proprietary closed
Comparison of real-time operating systems
Comparison_of_real-time_operating_systems
Research project into RISC-based microprocessor design
Berkeley RISC is one of two seminal research projects into reduced instruction set computer (RISC) based microprocessor design taking place under the Defense
Berkeley_RISC
Technology project funded by the Government of India
Technology supports it through its Digital India RISC-V initiative. Shakti processors are based on the RISC-V instruction set architecture (ISA). The processors
SHAKTI_(microprocessor)
General-purpose programming language
widely-used modern systems like ARM and x86-64, but also PowerPC, SPARC, MIPS, RISC-V, LoongArch64 and even the IBM z/Architectures (S390). The toolchain can
Zig_(programming_language)
Type of microprocessor developed in India
portfolio includes several indigenously-developed processors based on the RISC-V instruction set architecture (ISA). The India Microprocessor Development
VEGA_Microprocessors
Semiconductor device manufacturer
shareholder of Quintauris, a joint company with the goal of standardizing RISC-V ecosystem. In 2025, the Italian government was reportedly seeking greater
STMicroelectronics
Component of a computer's CPU
Retrieved 25 May 2019. Asanovic, Krste (2017). The RISC V Instruction Set Manual (PDF) (2.2 ed.). Berkeley: RISC-V Foundation. Power ISA (3.0B ed.). Austin: IBM
Control_unit
Linux distribution
an open-standard system and open-source software stack based on RISC-V, enabling RISC-V hardware and software "to be recognized as a mainstream instruction
Deepin
Topics referred to by the same term
Internet country code top-level domain for Solomon Islands sb, Store Byte, an RISC-V instruction Sun Belt Conference, an NCAA Division I conference Nike SB,
SB
Microkernel OS written in Rust
Current platform targets include 32-bit and 64-bit x86, AArch64, and 64-bit RISC-V. As of September 2024, the Redox repository had a total of 97 contributors
RedoxOS
Project in integrated circuit design
of the OpenLane and ChipIgnite projects, the open-source ecosystem for RISC-V System-on-Chip (SoC) designs has expanded rapidly and is now considered
OpenROAD_Project
Chinese semiconductor company
Its microcontrollers are based on the ARM architecture (GD32 series), and RISC-V architecture (GD32V series). GigaDevice Semiconductor was founded in 2005
GigaDevice
American system-on-chip technology company
The latest release of Ncore works with multiple processor IPs, including RISC-V and the next-generation Armv9 Cortex processor IP. Ncore boasts multi-protocol
Arteris
American multinational technology company
generations. On July 21, 2025, Nvidia announced to extend CUDA support to RISC-V. As of 2026, NVIDIA has over a 100 different open-source projects available
Nvidia
openpowerfoundation.org. 2020-05-01. Retrieved 2021-10-20. OpenPOWER EULA "RISC-V Ratified Specification". Retrieved 18 October 2025. Oracle SPARC Processor
Comparison of instruction set architectures
Comparison_of_instruction_set_architectures
Operating system built for microcontrollers
isolate components so untrusted third-party applications can run on Cortex-M, RISC-V, and x86 processors in a protected environment. Amit Levy, a PhD student
Tock_(operating_system)
Family of RISC-based computer processors
Argonaut RISC Core (ARC) is a family of 32-bit and 64-bit reduced instruction set computer (RISC) central processing units (CPUs) originally designed
ARC_(processor)
Components licensed as modules in larger integrated circuit designs
the ARM architectures or RISC-V architectures. Such processors form the "brains" of many embedded systems. They are usually RISC instruction sets rather
Semiconductor intellectual property core
Semiconductor_intellectual_property_core
Belgian international nonprofit association (AISBL)
Eclipse Foundation that aims to make open source RISC-V cores the global standard. It stewards RISC-V IP including CVA6, CVW (Wally), CVE4, CVE2, and CVE5
Eclipse_Foundation
Microcontroller software based on Python
MicroPython version 1.9.4. In 2017, Microsemi made a MicroPython port for RISC-V (RV32 and RV64) architecture. In April 2019, a version of MicroPython for
MicroPython
Machine instruction that indicates to a computer to do nothing
original on 28 December 2018. The RISC-V Instruction Set Manual, Volume 1: User-Level ISA, version 2.2 (PDF). RISC-V Foundation. 7 May 2017. p. 79. Weaver
NOP_(code)
Japanese technology corporation
Tenstorrent outsourced to Rapidus for production and development is based on RISC-V, and its benefits are close to what the university stakeholders, who are
Rapidus
GPU microarchitecture designed by Nvidia
Management Processor (AMP), a dedicated scheduler chip on the GPU built on RISC-V. It is designed to offload scheduling from the CPU to a greater degree than
Blackwell_(microarchitecture)
Quickly accessible working storage available as part of a digital processor
Instruction Set (PDF). RISC-V Foundation. March 12, 2001. Retrieved October 6, 2024. Waterman, Andrew; Asanovi, Krste, eds. (May 2017). The RISC-V, Instruction
Processor_register
Microprocessor core
terms of its instruction set architecture, MicroBlaze is similar to the RISC-based DLX architecture described in a popular computer architecture book
MicroBlaze
security: microkernels, ocap, RISC-V support". Retrieved 17 April 2020. "POWER (ppc64le) porting". Retrieved 11 January 2019. "RISC-V (riscv64) porting + multilib
Comparison of Linux distributions
Comparison_of_Linux_distributions
Reverse engineering software
code. It decompiles Dalvik bytecode to Java source code, and x86, ARM, RISC-V, and other machine code to C source code. The assembly and source outputs
JEB_decompiler
Microprocessor development project
OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer
OpenRISC
Computer operating system by Acorn Computers Ltd
RISC OS (/rɪsk.oʊˈɛs/) is an operating system designed to run on ARM computers. Originally designed in 1987 by Acorn Computers of England, it was made
RISC_OS
Assembly-language programming and binary-analysis tools
MSP430 assembly Parrot assembly language PIC assembly PowerPC assembly RISC-V assembly SPARC assembly Typed assembly language VAX MACRO 65C02 assembly
List of assembly software and tools
List_of_assembly_software_and_tools
Open source software driver for Nvidia GPU
4th RISC-V Workshop in July 2016 Nvidia employees introduced their plans to replace FALCON with a new proprietary custom design based on the RISC-V instruction
Nouveau_(software)
Open-source software
source BLAS library for multiple platforms, including x86, ARMv8, MIPS, and RISC-V platforms, and is respected for its excellent portability. The parallel
OpenBLAS
Software development kit
"Google's Flutter showcases new graphics capabilities, WebAssembly and RISC-V support". TechCrunch. Thomsen, Michael (2024-05-14). "Landing Flutter 3
Flutter_(software)
Topics referred to by the same term
RISC in Wiktionary, the free dictionary. RISC is an abbreviation for reduced instruction set computer. RISC or Risc may also refer to: Berkeley RISC Classic
RISC_(disambiguation)
Single board computer development board
Developers To Build RISC-V PCs For The First Time - RISC-V Foundation". 7 May 2018. "Hi-Five Unleashed: The first Linux-capable RISC-V single board computer
HiFive_Unleashed
Version 2.07, 3 May 2013, page 259. Archived on 7 Jan 2017. RISC-V International, The RISC-V Instruction Set Manual, Volume I, version 20260120 - see section
Carry-less_product
Family of RISC-based computer architectures
Arm (stylised in lowercase as arm) is a family of RISC instruction set architectures for computer processors. Arm Holdings develops the instruction set
Arm_architecture_family
RISC V
RISC V
Girl/Female
Latin
Laughter.
Boy/Male
Anglo Saxon
warrior.
Male
Hungarian
Hungarian form of Roman Latin Laurentius, LÖRINC means "of Laurentum."
Girl/Female
American, Australian, Danish, Japanese, Latin
Smile; Laughter
Boy/Male
Bengali, Indian
Honest and Clever
Boy/Male
Indian, Sanskrit
Sage; Saint; Brave and Dominant Ruler
Girl/Female
Hindu, Indian
Rise
Male
French
French form of Latin Fredericus, FRÉDÉRIC means "peaceful ruler."
Female
Greek
(ΛάÏισα) Greek name derived from the name of an ancient city, possibly LÃRISA means "fortified town."Â
Boy/Male
Czechoslovakian
Girl/Female
Hindu, Indian
Rise
Male
Hungarian
Hungarian form of Roman Latin Maurice, MÓRIC means "dark-skinned; Moor."
Boy/Male
Anglo, Australian, British, Danish, English, French, German, Italian, Norse, Swedish
Strong Ruler; Variant of Richard; Ruler; Dominant Ruler; Brother; Powerful Ruler
Boy/Male
Italian
Powerful; strong ruler.
Boy/Male
Hindu
To rise, Honest
Boy/Male
English
Rush
Boy/Male
Hindu
Brave & dominant ruler
Surname or Lastname
English
English : topographic name from Old English hrÄ«s ‘brushwood’, or a habitational name from Rise in East Yorkshire, named with this word.Norwegian : habitational name from any of over twenty farmsteads named Rise, from Old Norse hrÃs ‘brushwood’. The name also occurs in Sweden and Denmark.
Boy/Male
British, Czech, Czechoslovakian, English, German
Czechoslovakian Form of Richard
Boy/Male
Tamil
To rise, Honest
RISC V
RISC V
Boy/Male
Indian, Tamil
Self Protected
Boy/Male
Tamil
Sreenivasa | ஸà¯à®°à¯€à®¨à¯€à®µà®¾à®¸à®¾
Lord Venkateshwara, Residence of Goddess of wealth, Abode of wealth
Boy/Male
Australian, German, Italian
Famous in Battle
Boy/Male
Hindu, Indian
Quite New
Boy/Male
Irish Gaelic
Bright.
Girl/Female
Gujarati, Hindu, Indian
Blooming
Boy/Male
Tamil
Afiractive
Boy/Male
British, English
Lives Near the Church
Boy/Male
Tamil
Jyotirmoy | ஜà¯à®¯à¯‹à®¤à®¿à®°à®®à¯‹à®¯
Lustrous
Boy/Male
Tamil
Jaipreeth | ஜைபà¯à®°à®¿à®¤
The victory of Love, Loard of uganda
RISC V
RISC V
RISC V
RISC V
RISC V
v.
To become more and more dignified or forcible; to increase in interest or power; -- said of style, thought, or discourse; as, to rise in force of expression; to rise in eloquence; a story rises in interest.
n.
Spring; source; origin; as, the rise of a stream.
n.
Appearance above the horizon; as, the rise of the sun or of a planet.
v.
To ascend on a musical scale; to take a higher pith; as, to rise a tone or semitone.
n.
The distance through which anything rises; as, the rise of the thermometer was ten degrees; the rise of the river was six feet; the rise of an arch or of a step.
v.
To become erect; to assume an upright position; as, to rise from a chair or from a fall.
n.
Land which is somewhat higher than the rest; as, the house stood on a rise of land.
v.
To tower up; to be heaved up; as, the Alps rise far above the sea.
p. pr. & vb. n.
of Rise
v.
To leave one's bed; to arise; as, to rise early.
n.
To expose to risk, hazard, or peril; to venture; as, to risk goods on board of a ship; to risk one's person in battle; to risk one's fame by a publication.
p. pr. & vb. n.
of Risk
v. i.
To rise in value. [See note under Rise, v. i.]
v.
In various figurative senses.
n.
A circular structure either in plants or animals; as, a blood disc, a germinal disc, etc. Same as Disk.
n.
Elevation or ascent of the voice; upward change of key; as, a rise of a tone or semitone.
v.
To have a beginning; to proceed; to originate; as, rivers rise in lakes or springs.
n.
To incur the risk or danger of; as, to risk a battle.