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Methods used to implement electronic computer data storage
Memory architecture describes the methods used to implement electronic computer data storage in a manner that is a combination of the fastest, most reliable
Memory_architecture
Distributed computing architecture
A shared-memory architecture (SM) is a distributed computing architecture in which the nodes share the same memory as well as the same storage. It contrasts
Shared-memory_architecture
Computer architecture where code and data share a common bus
to transfer data between the memory and the outside recording medium. The attribution of the invention of the architecture to von Neumann is incorrect
Von_Neumann_architecture
Computer memory architecture
hardware, multi-channel memory architecture is a technology that increases the data transfer rate between the DRAM memory and the memory controller by adding
Multi-channel memory architecture
Multi-channel_memory_architecture
Computer memory design used in multiprocessing
reducing traffic on the memory bus. NUMA architectures logically follow in scaling from symmetric multiprocessing (SMP) architectures. They were developed
Non-uniform_memory_access
Computer instruction set architecture
engineering, a register–memory architecture is an instruction set architecture that allows operations to be performed on (or from) memory, as well as registers
Register–memory_architecture
Computer memory that can be accessed by multiple processes
access time depends on the memory location relative to a processor; cache-only memory architecture (COMA): the local memories for the processors at each
Shared_memory
32-bit RISC-like computing architecture
clearing the PSW, and loading the PC and SSW from a memory trap vector. The Clipper is a load/store architecture, where arithmetic operations could only specify
Clipper_architecture
Specialized electronic circuit that accelerates graphics
processors (IGP), or unified memory architectures (UMA) use a portion of a computer's system RAM rather than dedicated graphics memory. IGPs can be integrated
Graphics_processing_unit
System-on-a-chip series designed by Apple Inc.
to memory, which Apple says accelerates on-device Apple Intelligence features and other AI workloads. All M5 chips use a unified memory architecture that
Apple_M5
Form of computer memory
Hybrid Memory Cube List of RAM chip manufacturers List of RAM module manufacturers Memory geometry Memory module Multi-channel memory architecture RAM parity
Random-access_memory
Specialized microprocessor optimized for digital signal processing
because of power consumption constraints. DSPs often use special memory architectures that are able to fetch multiple data or instructions at the same
Digital_signal_processor
Set of rules describing computer system
It covers the instruction set architecture, CPU microarchitecture, memory, and input/output systems. Computer architecture also considers tradeoffs between
Computer_architecture
potential collisions in allocation. cache-only memory architecture (COMA) A multiprocessor memory architecture where an address space is dynamically shifted
Glossary of computer hardware terms
Glossary_of_computer_hardware_terms
Computing system
"ARM Bifrost GPU Architecture". 30 May 2016.{{cite web}}: CS1 maint: deprecated archival service (link) Computer memory architecture for hybrid serial
Heterogeneous System Architecture
Heterogeneous_System_Architecture
Type of instruction set architecture
load–store architecture (or a register–register architecture) is an instruction set architecture that divides instructions into two categories: memory access
Load–store_architecture
Hardware that translates virtual addresses to physical addresses
maximum memory of the computer architecture, 32 or 64 bits. The MMU maps the addresses from each program into separate areas in physical memory, which
Memory_management_unit
Computer memory organization
Cache only memory architecture (COMA) is a computer memory organization for use in multiprocessors in which the local memories (typically DRAM) at each
Cache-only memory architecture
Cache-only_memory_architecture
Computer memory architecture
computer science, distributed shared memory (DSM) is a form of memory architecture where physically separated memories can be addressed as a single shared
Distributed_shared_memory
Computer memory architecture
In computer architecture, the memory hierarchy separates computer storage into a hierarchy based on response time. Since response time, complexity, and
Memory_hierarchy
GPU for the PlayStation 3
based on the G70 architecture, but features a few changes to the core. The biggest difference between the two chips is the way the memory bandwidth works
RSX_Reality_Synthesizer
memory location. Big-endian architectures instead arrange bytes with the most significant byte at the lowest-numbered address. The x86 architecture as
Comparison of instruction set architectures
Comparison_of_instruction_set_architectures
Parallel computing memory architecture
Uniform memory access (UMA) is a shared-memory architecture used in parallel computers. All processors in the UMA model share their physical memory uniformly
Uniform_memory_access
Reference to a specific memory location
In computing, a memory address is a reference to a specific memory location in memory used by both software and hardware. These addresses are fixed-length
Memory_address
Computer architecture treating code and data similarly, though not usually identically
modified Harvard architecture is a variation of the Harvard computer architecture that, unlike the pure Harvard architecture, allows memory that contains
Modified_Harvard_architecture
Computer architecture where code and data each have a separate bus
with the von Neumann architecture, where program instructions and data share the same memory and pathways. The Harvard architecture is often used in real-time
Harvard_architecture
Type of distributed computing architecture
shared-nothing architecture (SN) is a distributed computing architecture in which each update request is satisfied by a single node (processor/memory/storage
Shared-nothing_architecture
Open source distributed database management system
function. The memory architecture in Apache Ignite consists of two storage tiers and is called "durable memory". Internally, it uses paging for memory space management
Apache_Ignite
Microprocessor instruction set architecture
IA-64 (Intel Itanium architecture) is the instruction set architecture (ISA) of the discontinued Itanium family of 64-bit Intel microprocessors. The basic
IA-64
Type of dedicated computer memory
relies instead on system RAM, is said to have a unified memory architecture, or shared graphics memory. System RAM and VRAM have been segregated due to the
Video_random-access_memory
Configuration in computer memory
memory management unit (IOMMU) is a memory management unit (MMU) connecting a direct-memory-access–capable (DMA-capable) I/O bus to the main memory.
Input–output memory management unit
Input–output_memory_management_unit
64-bit extension of the ARM architecture
version of the ARM architecture family, a widely used set of computer processor designs. It was introduced in 2011 with the ARMv8 architecture and later became
AArch64
Abstract machine for the execution of Prolog
an abstract machine for the execution of Prolog consisting of a memory architecture and an instruction set. This design became known as the Warren Abstract
Warren_Abstract_Machine
Family of RISC-based computer architectures
(execute never) bits have been added in VMSAv6 [Virtual Memory System Architecture] ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition. ARM Limited
ARM_architecture_family
Model that describes the programmable interface of a computer processor
instruction pipeline only allow a single memory load or memory store per instruction, leading to a load–store architecture (RISC). For another example, some
Instruction_set_architecture
System-on-a-chip designed by Apple Inc.
the M3 (compared to the previous generation M2). The M3's Unified Memory Architecture (UMA) is similar to the M2 generation; M3 SoCs use 6,400 MT/s LPDDR5
Apple_M3
Unix workstation from Silicon Graphics
as the "Moosehead" project, the O2 architecture features a proprietary high-bandwidth Unified Memory Architecture (UMA) to connect system components.
SGI_O2
GPU microarchitecture designed by Nvidia
Hopper architectures, 64. The Hopper architecture provides a Tensor Memory Accelerator (TMA), which supports bidirectional asynchronous memory transfer
Hopper_(microarchitecture)
Ninth and last major release of the classic Mac OS (1999)
the cooperative multitasking and memory architecture of earlier versions of the classic Mac OS, lacking protected memory and full pre-emptive multitasking
Mac_OS_9
Processor executing one instruction in minimal clock cycles
from memory to a register). The RISC computer usually has many (16 or 32) high-speed, general-purpose registers with a load–store architecture in which
Reduced instruction set computer
Reduced_instruction_set_computer
Quickly accessible working storage available as part of a digital processor
In computer architecture, registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g
Processor_register
GPU microarchitecture by Nvidia
of 720 GB/s. Unified memory — a memory architecture where the CPU and GPU can access both main system memory and memory on the graphics card with the help
Pascal_(microarchitecture)
Random-access memory with processing elements integrated on the same chip
efficiently use memory bandwidth within a memory chip. The general technique of doing computations in memory is called processing-in-memory (PIM). The most
Computational_RAM
Computer architecture bit width
In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit central processing units
64-bit_computing
Memory addressing limitation in 32-bit computers
to the memory limits of the early Intel 8088 IBM PC memory architecture (see Conventional memory). Similar situations have often arisen in the history
PCI_hole
Single chip microcontroller series by Intel
Wharton. The 8051 architecture provides many functions (central processing unit (CPU), random-access memory (RAM), read-only memory (ROM), input/output
Intel_MCS-51
Type of concurrency control mechanism
"Transactional memory: Architectural support for lock-free data structures" (PDF). Proceedings of the 20th International Symposium on Computer Architecture (ISCA)
Transactional_memory
Programming paradigm in which many processes are executed simultaneously
make about the underlying memory architecture—shared memory, distributed memory, or shared distributed memory. Shared memory programming languages communicate
Parallel_computing
GPU microarchitecture by Nvidia
DRAM: supported up to 6 GB of GDDR5 DRAM memory thanks to the 64-bit addressing capability (see Memory Architecture section). Clock frequency: 1.5 GHz (not
Fermi_(microarchitecture)
Type of memory used on processors that require high transfer rate memory
High Bandwidth Memory (HBM) is a computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM), initially developed by Samsung
High_Bandwidth_Memory
Processing data technology
(CIM) or processing-in-memory (PIM), is a computer architecture in which data operations are available directly on the data memory, rather than having to
In-memory_processing
Computer memory access architecture
waiting for memory banks to become ready for the operations. It is different from multi-channel memory architectures, primarily as interleaved memory does not
Interleaved_memory
graphics subsystem. This is called Unified Memory Architecture (UMA). Most early personal computers used a shared memory design. Such designs reduced costs as
Shared_graphics_memory
Computer internal interconnect architecture
of processors. Fireplane combines both, to give a scalable shared memory architecture. Each expander board implements snooping across the board, with directory
Fireplane
Set of memory models of the x86 CPU
registers are used to refer to four segments on the 16-bit x86 segmented memory architecture. DS (data segment), CS (code segment), SS (stack segment), and ES
X86_memory_models
Design of high-performance computers
connected to the largest amount of shared memory that could be managed at the time. These early architectures introduced parallel processing at the processor
Supercomputer_architecture
Storage of digital data readable by computers
to as "memory", while slower persistent components are referred to as "storage". This distinction was extended in the Von Neumann architecture, where
Computer_data_storage
Method of CPU communication
I/O is isolated from that for main memory, this is sometimes referred to as isolated I/O. On the x86 architecture, index/data pair is often used for port-mapped
Memory-mapped I/O and port-mapped I/O
Memory-mapped_I/O_and_port-mapped_I/O
Quantum instruction set architecture
Quil is a quantum instruction set architecture that first introduced a shared quantum/classical memory model. It was introduced by Robert Smith, Michael
Quil (instruction set architecture)
Quil_(instruction_set_architecture)
Computer feature
virtual memory above the basic processor architecture. The descriptor was an essential part of the development of the B5000 with automatic memory management
Burroughs large systems descriptors
Burroughs_large_systems_descriptors
Database system utilizing parallelization
first group of architecture is the multiprocessor architecture, the alternatives of which are the following: Shared-memory architecture Where multiple
Parallel_database
Vega architecture result in the PS4 Pro having a theoretical half precision floating point performance of 8.39 TeraFLOPs. Overall unified system memory architecture
PlayStation 4 technical specifications
PlayStation_4_technical_specifications
Subsystem of the Linux kernel
specifically designed with an UMA memory architecture in mind, making them less suitable for other memory architectures like those with a separate VRAM
Direct_Rendering_Manager
Equal sharing of all resources by multiple identical processors
multiprocessing or shared-memory multiprocessing (SMP) involves a multiprocessor computer hardware and software architecture where two or more identical
Symmetric_multiprocessing
64-bit extension of x86 architecture
virtual and physical memory compared to its 32-bit predecessors, allowing computer programs to utilize more memory. The architecture increases the number
X86-64
Component that stores information
located in computer memory. The terms memory, main memory, and primary storage are also used for computer memory. Computer memory is often referred to
Computer_memory
Division of computer's primary memory into separately relocatable segments or sections
Memory segmentation is an operating system memory management technique of dividing a computer's primary memory into segments or sections. In a computer
Memory_segmentation
RISC instruction set architecture
SPARC (Scalable Processor ARChitecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems
SPARC
Discontinued computer memory type
XPoint architecture differs from previous offerings of PCM and uses chalcogenide materials for both selector and storage parts of the memory cell that
3D_XPoint
Way to control memory access rights on a computer
Memory protection is a way to control memory access rights on a computer, and is a part of most modern instruction set architectures and operating systems
Memory_protection
Hypothetical consciousness in artificial systems
IDA, these two memories are implemented computationally using a modified version of Kanerva's sparse distributed memory architecture. Learning is also
Artificial_consciousness
Third generation of double-data-rate synchronous dynamic random-access memory
Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high-bandwidth ("double
DDR3_SDRAM
IBM computer family (1964–1977)
violating architectural definitions: the 65 had a dual-processor version (M65MP) with extensions for inter-CPU signalling; the 85 introduced cache memory. Models
IBM_System/360
In computing, a mapped memory location
may be, in the case of a computer memory architecture, a memory management unit (MMU) between the CPU and the memory bus. There may be more than one level
Logical_address
Blueprint for intelligent agents
& Bower G H. Human associative memory. Washington," in: CC. Nr. 52 Dec 24–31, 1979. John R. Anderson. The Architecture of Cognition, 1983/2013. Vernon
Cognitive_architecture
Access latency of a memory unit from RAM
time. Burst mode (computing) CAS latency Multi-channel memory architecture Interleaved memory SDRAM burst ordering SDRAM latency Crucial Technology, "Speed
Memory_latency
Memory hierarchy concept applied to CPU caches with multiple levels
Cache hierarchy, or multi-level cache, is a memory architecture that uses a hierarchy of memory stores based on varying access speeds to cache data. Highly
Cache_hierarchy
Electronic non-volatile computer storage device
directly. Its architecture allows for individual byte access, facilitating faster read speeds compared to NAND flash. NAND flash memory operates with
Flash_memory
Computer storage device with no moving parts
cells, with the specific architecture influencing performance, endurance, and cost. There are various types of NAND flash memory, categorized by the number
Solid-state_drive
Topics referred to by the same term
UMa in Wiktionary, the free dictionary. UMA may refer to: Unified memory architecture, a synonym of "integrated graphics", in computer graphics processing
UMA
Distributed computing architecture
shared-disk architecture (SD) is a distributed computing architecture in which the nodes share same disk devices but each node has its own private memory. The
Shared-disk_architecture
into the x86 architecture with the Pentium II Xeon and was initially advertised as part of the "Intel Extended Server Memory Architecture" (sometimes abbreviated
PSE-36
a server architecture which laid the foundation for Sun Microsystems' NUMA machines, technologies to minimize (leakage) power in the memory system in
Babak_Falsafi
High-end IBM computer model from 1960s
It was also one of the first computers to utilize multi-channel memory architecture. Castells-Rufas et al. reported that the 360/91 used 74kW of power
IBM_System/360_Model_91
PIC family of controllers, produced by Microchip Technology. The memory architecture makes use of bank switching. Software tools for assembler, debug
PIC16x84
Multiple of the unit byte
the prevalence of sizes that are powers of two in modern digital memory architectures, coupled with the coincidence that 210 differs from 103 by less than
Kilobyte
Series of GPUs by Nvidia
better advantage of available memory performance, the GeForce 3 has a memory subsystem dubbed Lightspeed Memory Architecture (LMA). This is composed of several
GeForce_3_series
Computer memory management scheme
instruction set architecture (ISA) for instance, the memory paging is enabled via the CR0 control register. In the 1960s, swapping was an early memory management
Memory_paging
Message-passing system for parallel computers
has advantages when running on NUMA architectures, since MPI encourages memory locality. Explicit shared-memory programming was introduced in MPI-3.
Message_Passing_Interface
Family of instruction set architectures
eight-bit 8008 and 8080 architectures. Byte-addressing is enabled and words are stored in memory with little-endian byte order. Memory access to unaligned
X86
Part of computer memory
including core memory, twistor memory, and bubble memory. Today[as of?], the most common memory cell architecture is MOS memory, which consists of metal–oxide–semiconductor
Memory_cell_(computing)
Instruction set architecture
instruction stream to reduce the memory programs require; and MIPS MT, which adds multithreading capability. Computer architecture courses in universities and
MIPS_architecture
Processor with instructions capable of multi-step operations
architecture in which single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory
Complex instruction set computer
Complex_instruction_set_computer
Multiprocessing memory architecture
computer science, distributed memory refers to a multiprocessor computer system in which each processor has its own private memory. Computational tasks can
Distributed_memory
US DOE supercomputer by Intel and Cray
and a unified memory architecture, providing a maximum computing power of 130 teraFLOPS per node. It has around 10 petabytes of memory and 230 petabytes
Aurora_(supercomputer)
Fixed-length contiguous block of virtual memory
on the architecture) for the correct mapping. Larger page sizes mean that a TLB cache of the same size can keep track of larger amounts of memory, which
Page_(computer_memory)
Type of computer memory
random-access memory (dynamic RAM or DRAM) is a type of random-access semiconductor memory that stores each bit of data in a memory cell. A DRAM memory cell usually
Dynamic_random-access_memory
CPU socket for AMD processors with Zen and Excavator architectures
platform. It has 1331 pin slots and is the first from AMD to support DDR4 memory as well as achieve unified compatibility between high-end CPUs (previously
Socket_AM4
Chinese semiconductor company
Xtacking architecture designed for Vertical NAND chips at the Flash Memory Summit, receiving the "Best of Show" award for "Most Innovative Flash Memory Start-up
Yangtze_Memory_Technologies
Brand of GPUs by Nvidia
1050 use GDDR5. Unified memory – A memory architecture, where the CPU and GPU can access both main system memory and memory on the graphics card with
GeForce
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