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Set of memory models of the x86 CPU
In computing, the x86 memory models are a set of six different memory models of the x86 CPU operating in real mode which control how the segment registers
X86_memory_models
Memory segmentation on Intel x86
x86 memory segmentation is a term for the kind of memory segmentation characteristic of the Intel x86 computer instruction set architecture. The x86 architecture
X86_memory_segmentation
Topics referred to by the same term
Paged memory model Segmented memory One of the x86 memory models This disambiguation page lists articles associated with the title Memory model. If an
Memory_model
Computer memory addressing model
all subsequent x86 machines through to present day Pentium and Core 2 processors. This memory model has remained ever since in the x86 machines, which
Flat_memory_model
64-bit extension of x86 architecture
four-level paging mechanism. In 64-bit mode, x86-64 supports significantly larger amounts of virtual and physical memory compared to its 32-bit predecessors,
X86-64
Family of backward-compatible assembly languages
x86 assembly language is a family of low-level programming languages that are used to produce object code for the x86 class of processors. Previous evolutions
X86_assembly_language
Calling conventions used in x86 architecture programming
This article describes the calling conventions used when programming x86 architecture microprocessors. Calling conventions describe the interface of called
X86_calling_conventions
Family of instruction set architectures
microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being
X86
Hardware-assisted virtualization on x86/x86-64 CPUs
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved
X86_virtualization
List of x86 microprocessor instructions
(32-bit) x86 and (64-bit) x86-64 (also known as AMD64). This is the original instruction set. In the 'Notes' column, r means register, m means memory address
List_of_x86_instructions
Processor extension for the x86-64 line of processors
the memory manager has to access physical memory six times for a single virtual memory access, rather than five for the previous iteration of x86-64 processors
Intel_5-level_paging
Open-source software library for LLM inference
library that performs inference on various large language models such as Meta's Llama model. It is co-developed alongside the GGML project, a general-purpose
Llama.cpp
Order of accesses to computer memory by a CPU
used architectures, x86-64 processors have the strongest memory order, but may still defer memory store instructions until after memory load instructions
Memory_ordering
Reference to a specific memory location
instructions run slower. Early x86 processors use the segmented memory model addresses based on a combination of two numbers: a memory segment, and an offset
Memory_address
Memory management feature
sometimes referred to as Page Address Extension, is a memory management feature for the x86 architecture. PAE was first introduced by Intel in the Pentium
Physical_Address_Extension
Hardware that translates virtual addresses to physical addresses
physical memory (and memory-mapped i/o). (Optional expanded memory hardware can add bank-switched memory under software control.) Later x86 processors
Memory_management_unit
Computer architecture bit width
with 64-bit virtual memory addresses. However, not all 64-bit instruction sets support full 64-bit virtual memory addresses; x86-64 and AArch64, for example
64-bit_computing
System of bank switching in DOS memory management
Extended memory (XMS) High memory area (HMA) Overlay (programming) Upper memory area (UMA) Global EMM Import Specification (GEMMIS) x86 memory segmentation
Expanded_memory
32-bit microprocessor by Intel
microprocessor introduced by Intel in 1985 as the third generation of the x86 processor family. It extended the architecture with 32-bit registers and
I386
Division of computer's primary memory into separately relocatable segments or sections
Flat memory model Memory management (operating systems) Segmentation fault Virtual address space Virtual memory x86 memory segmentation Models 115, 125
Memory_segmentation
Computing term
stack memory, without moving the stack pointer, which saves an instruction. Whether a red zone is present depends on the calling convention. x86-64 systems
Red_zone_(computing)
Method of CPU communication
space for I/O is isolated from that for main memory, this is sometimes referred to as isolated I/O. On the x86 architecture, index/data pair is often used
Memory-mapped I/O and port-mapped I/O
Memory-mapped_I/O_and_port-mapped_I/O
Layer of protection in computer systems
and also enforces restrictions on the types of memory access that can be performed across rings. Using x86 as an example, there is a special[clarification
Protection_ring
Free virtualization and emulation software
i386 and x86_64 architectures. Besides the central processing unit (CPU) (which is also configurable and can emulate a number of Intel CPU models including
QEMU
Instruction for x86 microprocessors
In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from "CPU Identification")
CPUID
Consistency model in concurrent computing
consistency is one of the consistency models used in the domain of concurrent computing (e.g. in distributed shared memory, distributed transactions, etc.)
Processor_consistency
Computer architecture bit width
servers have moved on to 64 bits using architectures such as x86-64, with installed memory in entry-level computers often exceeding the 32-bit address
32-bit_computing
Line of Intel server and workstation processors
and x86-64 processors. The P6-based models added the Xeon moniker to the end of the name of their corresponding desktop processor, but all models since
Xeon
Virtual reality headset
software, as well as additional compatibility layers for Android software and x86-64 code), or streamed wirelessly from a PC over a local network using Steam
Steam_Frame
Instructions directly executable by a computer
interface to a CPU and varies by groupings or families of CPU design such as x86 and ARM. Generally, machine code compatible with one family is not with others
Machine_code
Variant of real mode in x86 computing
entire memory. Contrary to its name, it is not a separate addressing mode that the x86 processors can operate in. It is used in the 80286 and later x86 processors
Unreal_mode
Computer memory design used in multiprocessing
Non-uniform memory access (NUMA) is a computer memory design used in multiprocessing, where the memory access time depends on the memory location relative
Non-uniform_memory_access
Computer programming language
assembly language within Pascal source code. Support for the various x86 memory models was provided by inline assembly, compiler options, and language extensions
Turbo_Pascal
Fifth generation of Intel Core processors
microarchitecture designed by Intel, based on the x86-64 instruction set. As a "tick" generation of the company's tick–tock model, Broadwell is a die shrink of its predecessor
Broadwell_(microarchitecture)
Control registers in some x86 processors
A model-specific register (MSR) is any of various control registers in the x86 system architecture used for debugging, program execution tracing, performance
Model-specific_register
Software for simulating computer architecture
architectures (ISAs), including x86, Arm, RISC-V, MIPS, SPARC, and Power, as well as a range of processor and memory-system models. Simulated systems are configured
Gem5
Memory data structure in Intel processors
Global Descriptor Table (GDT) is a core part of Intel's x86 architecture that helps manage how memory is accessed and protected. Introduced with the Intel
Global_Descriptor_Table
Computer memory management scheme
system's kernel. In CPUs implementing the x86 instruction set architecture (ISA) for instance, the memory paging is enabled via the CR0 control register
Memory_paging
Methods for dividing computing resources
x86 processors to support these extensions were released in late 2005 early 2006: On November 13, 2005, Intel released two models of Pentium 4 (Model
Virtualization
Computer memory management technique
policies Memory management Memory management (operating systems) Memory-mapped file Protected mode, an x86 mode that allows for virtual memory. CUDA pinned
Virtual_memory
Eleventh generation of Microsoft Surface Pro
(45 TOPS) Intel x86-based Intel Arc Xe² integrated GPU Intel® AI Boost NPU (40-48 TOPS) Up to 1TB of SSD storage, Up to 64GB of memory 13-inch touchscreen
Surface_Pro_11th_Edition
version with an 8-bit bus. 286 first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by
List of Intel CPU microarchitectures
List_of_Intel_CPU_microarchitectures
1.5 TB of DDR5 RDIMM 8000MT/s RAM and ECC memory. Underlined models support Intel Speed Select. All models are E-Core only. Announced at CES 2026 on January
List_of_Intel_processors
Consistency model in concurrent computing
instruction set architectures, including x86, x86-64, ARM, and RISC-V, do not present a sequentially consistent memory model to programs. Some important hardware
Sequential_consistency
SSE All models support: MMX, SSE Family 6 model 11 Family 15 model 1 All models support: MMX, SSE, SSE2 Steppings: E0 Family 15 model 2 All models support:
List of Intel Celeron processors
List_of_Intel_Celeron_processors
ARM-based system-on-chip by Nvidia
and developers and includes 128 GB of unified memory, allowing it to run inference workloads using models with up to 200 billion parameters locally. Several
Nvidia_RTX_Spark
Successor to the Intel 386
compatibility with software for earlier x86 processors. It was the first tightly-pipelined x86 design as well as the first x86 chip to include more than one million
I486
Operating mode of all x86-compatible CPUs
mode of all x86-compatible CPUs. The mode gets its name from the fact that addresses in real mode always correspond to real locations in memory. Real mode
Real_mode
Processor design concept
lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory addresses to physical memory addresses. It is used to reduce
Translation_lookaside_buffer
2013 processor microarchitecture
Haswell implements the x86-64 instruction set, which is the 64-bit variant of x86. It is the tock part of Intel's Tick–tock model, the stage where new architectural
Haswell_(microarchitecture)
AMD brand of server microprocessors
Epyc (stylized as EPYC) is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced
Epyc
Instruction set architecture extension
Instructions (TSX-NI), is an extension to the x86 instruction set architecture (ISA) that adds hardware transactional memory support, speeding up execution of multi-threaded
Transactional Synchronization Extensions
Transactional_Synchronization_Extensions
contents in memory (shadow ROM), and the configuration of memory-mapped I/O. In early x86 architecture systems, especially where the cache was provided
Memory_type_range_register
American multinational semiconductor company
of a 64-bit extension to the x86 instruction set (called x86-64, AMD64, or x64), the incorporation of an on-chip memory controller, and the implementation
AMD
Full-screen debugger for DOS by Microsoft
described as "a fullscreen SYMDEB". Borland Turbo Debugger SoftICE x86 memory models Microsoft Visual Studio Debugger Program database - CodeView formats
CodeView
Computer buffer holding data to be written
are written to main memory when the cache is written. Owens, Scott, Susmit Sarkar, and Peter Sewell. "A better x86 memory model: x86-TSO." Theorem Proving
Write_buffer
Device controlling access and addressing of memory
processors are also integrated memory management unit (MMU), which in many operating systems implements virtual addressing. On early x86-32 processors, the MMU
Memory_controller
16-bit microprocessor
16-bit microprocessor introduced by Intel in June 1978. It established the x86 instruction set architecture (ISA), which subsequent generations of processors
Intel_8086
Status register of x86 architecture
processor model. However, the above method remains useful to distinguish between earlier models. Bit field Control register CPU flag (x86) Program status
FLAGS_register
Operating system component
efficiency is the support of x86-64 memory ordering in the M1 SoC. The SoC also has dedicated instructions for computing x86 flags. Since macOS Ventura
Rosetta_(software)
Computer machine code instruction
new "Halt and Catch Fire" instruction on an undisclosed x86 processor model using his own x86 processor fuzzer called sandsifter. The NMOS MOS Technology
Halt and Catch Fire (computing)
Halt_and_Catch_Fire_(computing)
Intel processor microarchitecture
The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, first implemented in the Pentium Pro microprocessor in 1995. It was partially
P6_(microarchitecture)
(list of models) Industrial System (list of models) PCradio (list of models) Ambra (list of models) PS/note (list of models) EduQuest (list of models) ThinkPad
List of IBM Personal Computer models
List_of_IBM_Personal_Computer_models
2026 laptop by Microsoft
CPU-heavy titles such as Gears of War: E-Day, which run through Windows' Prism x86 emulator rather than natively on the Arm chip, struggled to use the GPU fully
Surface_Laptop_Ultra
Family of 64-bit Intel microprocessors
own x86-based processors. These designs can run existing 32-bit applications at native hardware speed, while offering support for 64-bit memory addressing
Itanium
Way for programs to access kernel services
located in a different segment than the current code segment) which uses x86 memory segmentation and the resulting lack of portability it causes, and the
System_call
X86-compatible system-on-a-chip
is a computing system-on-a-chip (SoC) based on a core compatible with the x86 microprocessor family. It is produced by DM&P Electronics, but originated
Vortex86
Computer memory management instruction
processor instruction set architectures, such as ARM, MIPS, PowerPC, and x86. Also termed data cache block touch, the effect is to request loading the
Cache_control_instruction
Type of cryptographic algorithm
cryptography, a memory-hard function (MHF) is a function that costs a significant amount of memory to efficiently evaluate. It differs from a memory-bound function
Memory-hard_function
Intel microprocessor series released in 2024
designs. Intel said that with Lunar Lake, it aimed to "bust the myth that [x86] can't be as efficient" as ARM. Analysis of tests performed on Lunar Lake
Lunar_Lake
2024 AMD 4-nanometer processor microarchitecture
respectively. Models with "F" suffixes are without iGPUs. L1 cache: 80 KB (48 KB data + 32 KB instruction) per core. L2 cache: 1 MB per core. Models with an
Zen_5
FP4 / FT4 2 "Excavator+" x86 CPU cores L1 Cache: 32 KB Data per core and 96 KB Instructions per module Single-channel DDR4 memory controller MMX, SSE, SSE2
List of AMD processors with 3D graphics
List_of_AMD_processors_with_3D_graphics
Computer memory architecture
all memory modules at the speed of the slowest module. Some motherboards, however, have compatibility issues with certain brands or models of memory when
Multi-channel memory architecture
Multi-channel_memory_architecture
Computer synchronizing instruction
instruction is used. In the case of the x86 architecture, the MFENCE, LFENCE, and SFENCE instructions are used. Memory barrier instructions address reordering
Memory_barrier
Concept in computer architecture
following form: The x86 and x86-64 segment descriptor has the following form: What the fields stand for: Base Address Starting memory address of the segment
Segment_descriptor
Line of Nvidia produced servers and workstations
systems typically come in a rackmount format, initially using high-performance x86 server CPUs, switching to ARMs around 2018, and releasing NUCs in 2025. The
Nvidia_DGX
Series of x86 manycore processors from Intel
Xeon Phi is a discontinued series of x86 manycore processors designed and made by Intel. It was intended for use in supercomputers, servers, and high-end
Xeon_Phi
Feature of computer systems
of device bandwidths). A modern x86 CPU may use more than 4 GB of memory, either utilizing the native 64-bit mode of x86-64 CPU, or the Physical Address
Direct_memory_access
Intel microprocessor family, released in 2020
memory, and double the UPI links over Cascade Lake. Cooper Lake is the first x86 CPU to support the new bfloat16 instruction set as a part of Intel's Deep
Cooper_Lake_(microprocessor)
Computer processor
Its hardware consists of x86 Linux hosts with vector engines (VEs) connected via PCI express (PCIe) interconnect. High memory bandwidth (0.75–1.2 TB/s)
NEC_SX-Aurora_TSUBASA
6th generation Xeon x86 server processors designed by Intel, released in 2024
6900P-series models today, with five new models spanning from 72 cores up to 128 cores, ... Intel will launch the more general-purpose P-core Xeon 6 models with
Granite_Rapids
CPU optimization unit
is visible, and needs to be taken into account by the programmer. When an x86 processor changes mode from real mode to protected mode and vice versa, the
Prefetch_input_queue
Computer fault caused by access to restricted memory
access a restricted area of memory (a memory access violation). On standard x86 computers, this is a form of general protection fault. The operating system
Segmentation_fault
Technical specification for firmware architecture
official documentation for the following processor architectures: x86 (IA-32, x86-64) Itanium (IA-64) ARM (AArch32, AArch64) RISC-V (32-bit, 64-bit,
UEFI
Instructions for the x86 microprocessors
Wikibooks has a book on the topic of: X86 Assembly/AVX, AVX2, FMA3, FMA4 Advanced Vector Extensions (AVX, also known as Gesher New Instructions and then
Advanced_Vector_Extensions
Processor with instructions capable of multi-step operations
include the Motorola 6800, 6809 and 68000 families; the Intel 8080, iAPX 432, x86 and 8051 families; the Zilog Z80, Z8 and Z8000 families; the National Semiconductor
Complex instruction set computer
Complex_instruction_set_computer
Capabilities of a computer architecture
x86, do not meet these conditions, so they cannot be virtualized in the classic way. But architectures can still be fully virtualized (in the x86 case
Popek and Goldberg virtualization requirements
Popek_and_Goldberg_virtualization_requirements
Server series by Sun Microsystems
while x86-64 based machines were marketed until mid-2012. In mid-2012, Oracle Corporation ceased to use the Sun Fire brand for new server models. UltraSPARC-based
Sun_Fire
processors, it supports a fully integrated memory controller, a HyperTransport IO bus, and the NX bit, or no-execute x86 extension to PAE mode. The Efficeon
Transmeta_Efficeon
Unconditional jump instruction in x86 assembly language
In the x86 assembly language, the JMP instruction performs an unconditional jump. Such an instruction transfers the flow of execution by changing the
JMP_(x86_instruction)
General-purpose programming language
programming language that emphasizes performance, type safety, concurrency, and memory safety. Rust supports multiple programming paradigms. It was influenced
Rust_(programming_language)
Microprocessors of the Ryzen brand are a line of x86-64 microprocessors manufactured by AMD, based on the Zen microarchitecture. Ryzen microprocessors
List_of_AMD_Ryzen_processors
Line of business-oriented laptop computers by Dell
a netbook. Dell used the "E-series" name up through the 2016 models, and new 2017 models drop the "E." and Dell E-Port Replicator with it. Latitude computers
Dell_Latitude
Collaborative Apple Computer and Novell prototype operating system
the DR DOS BIOS, BDOS kernel, device drivers, memory managers and the multitasker were written in pure x86 assembly language. Apple's port of System 7.1
Star_Trek_project
Function of computer operating systems
region terminates. Base and bounds Memory overcommitment Memory protection Region-based memory management x86 memory segmentation Known as TSO regions
Memory management (operating systems)
Memory_management_(operating_systems)
Operational mode of x86-compatible CPUs
operational mode of x86-compatible central processing units (CPUs). It allows system software to use features such as segmentation, virtual memory, paging and
Protected_mode
Intel Atom is Intel's line of low-power, low-cost and low-performance x86 and x86-64 microprocessors. Atom, with codenames of Silverthorne and Diamondville
List_of_Intel_Atom_processors
Open64 is a free, open-source, optimizing compiler for the Itanium and x86-64 microprocessor architectures. It derives from the SGI compilers for SGI's
Open64
Piece of software or hardware that creates and runs virtual machines
imposes a further requirement for small memory-size and low overhead. Finally, in contrast to the ubiquity of the x86 architecture in the PC world, the embedded
Hypervisor
Trusted execution environment subsystem that runs on AMD microprocessors
and load UEFI firmware within the SPI ROM, thus starting x86 cores. While UEFI firmware and x86 cores is started, the PSP still do some hardware initialization
AMD Platform Security Processor
AMD_Platform_Security_Processor
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X86 MEMORY-MODELS
X86 MEMORY-MODELS
X86 MEMORY-MODELS
X86 MEMORY-MODELS
X86 MEMORY-MODELS
X86 MEMORY-MODELS
X86 MEMORY-MODELS
X86 MEMORY-MODELS
X86 MEMORY-MODELS
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