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Process used to make microchips
The planar process is a manufacturing process used in the semiconductor industry to build individual components of a transistor, and in turn, connect
Planar_process
The first planar monolithic integrated circuit (IC) chip was demonstrated in 1960. The idea of integrating electronic circuits into a single device was
Invention of the integrated circuit
Invention_of_the_integrated_circuit
Swiss-born American engineer (1924–1997)
transistor pioneer, and a member of the "traitorous eight". He developed the planar process, an important technology for reliably fabricating and manufacturing
Jean_Hoerni
Manufacturing process used to create integrated circuits
his senior staff, including Jean Hoerni, who would later invent the planar process in 1959 while at Fairchild Semiconductor. In 1948, Bardeen patented
Semiconductor device fabrication
Semiconductor_device_fabrication
Topics referred to by the same term
bitplanes Planar (transmission line technologies), transmission lines with flat conductors Planar, the structure resulting from the planar process used in
Planar
American integrated circuit manufacturer
Noyce's invention was enabled by the planar process developed by Jean Hoerni. In turn, Hoerni's planar process was inspired by the surface passivation
Fairchild_Semiconductor
Electronic circuit formed on a small, flat piece of semiconductor material
monolithic integrated circuit chip was enabled by the inventions of the planar process by Jean Hoerni and of p–n junction isolation by Kurt Lehovec. Hoerni's
Integrated_circuit
passivation by silicon dioxide and used their finding to create the first planar transistors, the first in which drain and source were adjacent at the same
History_of_the_transistor
Programmable machine that processes data
was fabricated using the planar process, developed by his colleague Jean Hoerni in early 1959. In turn, the planar process was based on Carl Frosch and
Computer
American physicist and entrepreneur (1927–1990)
Noyce's monolithic IC was the planar process, developed in early 1959 by Jean Hoerni. In turn, the basis for Hoerni's planar process were the silicon surface
Robert_Noyce
American electronics engineer (1937–1991)
adjustments in fabrication processes. This early work, directed by process engineer David Talbert, reduced the cost of the planar process and made possible development
Bob_Widlar
Computer-based technologies
the first planar silicon dioxide transistors by Frosch and Derick in 1957, the MOSFET demonstration by a Bell Labs team, the planar process by Jean Hoerni
Information_technology
Type of field-effect transistor
his senior staff, including Jean Hoerni, who would later invent the planar process in 1959 while at Fairchild Semiconductor. After this, J.R. Ligenza and
MOSFET
History of semiconductor light source
semiconductor chips fabricated with the planar process (developed by Jean Hoerni, ). The combination of planar processing for chip fabrication and innovative
History_of_the_LED
Industrial shift to information technology
Robert Noyce at Fairchild Semiconductor in 1959, made possible by the planar process developed by Jean Hoerni. In 1963, complementary MOS (CMOS) was developed
Information_Age
Type of transistor
characteristics over time. The planar transistor was developed by Dr. Jean Hoerni at Fairchild Semiconductor in 1959. The planar process used to make these transistors
Diffused_junction_transistor
Electronic circuits that utilize digital signals
his senior staff, including Jean Hoerni, who would later invent the planar process in 1959 while at Fairchild Semiconductor. At Bell Labs, J.R. Ligenza
Digital_electronics
Integrated circuit
integrated circuit was enabled by the planar process developed by Jean Hoerni. In turn, Hoerni's planar process was inspired by the surface passivation
Mixed-signal integrated circuit
Mixed-signal_integrated_circuit
Oxide of silicon
transistors (MOSFETs) and silicon integrated circuit chips (with the planar process). Hydrophobic silica is used as a defoamer component. In its capacity
Silicon_dioxide
Physical structure guiding light waves
rectangular geometry are produced by a variety of means, usually by a planar process.[citation needed] The field distribution in a rectangular waveguide
Waveguide_(optics)
Puzzle computer game involving planar graphs
Planarity is a 2005 puzzle computer game by John Tantalo, based on a concept by Mary Radcliffe at Western Michigan University. The name comes from the
Planarity
Engineering discipline specializing in the design of computer hardware
Frosch and Lincoln Derick, the first planar silicon dioxide transistors by Frosch and Derick in 1957, planar process by Jean Hoerni, the monolithic integrated
Computer_engineering
American scientist (1908–1984)
Hoerni, while working at Fairchild Semiconductor, had first patented the planar process in 1959. Frosch and Derrick build several silicon dioxide field effect
Carl_Frosch
American physicist and silicon pioneer (1929–2021)
describing his "Planar process". He presented a novel adaptation of silicon manufacturing processes that had originated at Bell Labs. The planar process created
Jay_Last
Interconnection 1958 – The Trans-Canada Microwave System 1959 – Semiconductor planar process by Jean Hoerni and silicon integrated circuit by Robert Noyce 1959 –
List_of_IEEE_Milestones
Fairchild's planar process, which allowed integrated circuits to be laid out using the same principles as those of printed circuits. The planar process was developed
History of computing hardware (1960s–present)
History_of_computing_hardware_(1960s–present)
Technique for drawing non-planar graphs
graph drawing methods from planar graphs to graphs that are not planar, by embedding the non-planar graphs within a larger planar graph. Planarization may
Planarization
High-gain voltage amplifier with a differential input
1954, the concept of ICs became a reality. The introduction of the planar process in 1959 made transistors and ICs stable enough to be commercially useful
Operational_amplifier
Fairchild's planar process, which allowed integrated circuits to be laid out using the same principles as those of printed circuits. The planar process was developed
History_of_computing_hardware
Research and scientific development company
the work of C. Frosch and L. Derick, and developed a process similar to Hoerni's planar process about the same time. J.R. Ligenza and W.G. Spitzer studied
Bell_Labs
Semiconductor manufacturing process
Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). Sub-10-nm planar-bulk-CMOS devices using lateral junction control. IEEE International Electron
3_nm_process
silicon transistors, built by Fairchild Semiconductor, that used the planar process. These did not have the drawbacks of the mesa silicon transistors. He
History_of_supercomputing
Graph formed by subdivision of triangles
by a process of recursively subdividing a triangle into three smaller triangles. Apollonian networks may equivalently be defined as the planar 3-trees
Apollonian_network
American technology company
20 nm planar process. At the same time it announced an UltraScale SoC architecture, called Zynq UltraScale+ MPSoC, in TSMC 16 nm FinFET process. In March
Xilinx
Central computer component that executes instructions
A central processing unit (CPU), also known as a central processor, main processor, or simply processor, is the primary processor in a given computer
Central_processing_unit
German optics company
(9×12 cm fmt) Planar lenses (5 elements in 4 groups) Planar 80mm ƒ/2.8 (6×7 cm fmt) Planar 100mm ƒ/2.8 (6.5×9 cm fmt) Planar 135mm ƒ/3.5 Planar 135mm ƒ/3
Zeiss_(company)
circuit in 1959, his idea of p–n junction isolation was based on Hoerni's planar process. In 1976, Noyce stated that, in January 1959, he did not know about
P–n_junction_isolation
Area of discrete mathematics
planar straight-line graph. Any planar graph can be represented as a planar straight-line graph by Fáry's theorem. The planar straight-line graph is the special
Graph_theory
Instructions a computer can execute
crystal. The crystal is then thinly sliced to form a wafer substrate. The planar process of photolithography then integrates unipolar transistors, capacitors
Computer_program
MOS field-effect transistor with more than one gate
architecture (planar vs. non-planar design) and the number of channels/gates (2, 3, or 4). A planar double-gate MOSFET (DGMOS) employs conventional planar (layer-by-layer)
Multigate_device
Geometric graph with unit edge lengths
in which no edges cross. Every matchstick graph is a planar graph, but some otherwise-planar unit distance graphs (such as the Moser spindle) have a
Unit_distance_graph
Device which converts input forces and motion to output forces and motion
called a planar mechanism. The kinematic analysis of planar mechanisms uses the subset of Special Euclidean group SE, consisting of planar rotations
Mechanism_(engineering)
Electronic component that exploits the electronic properties of semiconductor materials
his senior staff, including Jean Hoerni, who would later invent the planar process in 1959 while at Fairchild Semiconductor. After this, J.R. Ligenza and
Semiconductor_device
Type of non-planar transistor
performance—over planar transistors. Commercially produced chips at 22 nm and below have generally utilised FinFET gate designs (but planar processes do exist
Fin_field-effect_transistor
MOSFET technology node
"10 nm" processes are based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution
10_nm_process
American electrical engineer
semiconductor technologies such as the MOSFET (Mohamed Atalla and Dawon Kahng), planar process (Jean Hoerni), EPROM (Dov Frohman) and molecular-beam epitaxy (Alfred
Frank_Wanlass
Autodesk Revit, and FreeCAD. To visualise the process, consider the lofting process in boat building: the planar sections are defined by boat ribs spaced along
Loft_(3D)
Semiconductor foundry company
14LPP FinFET process from Samsung Electronics. In 2018 GlobalFoundries developed the 12 nm 12LP node based on Samsung's 14 nm 14LPP process. On 27 August
GlobalFoundries
American physicist (1936–2024)
device. In the late 1950s, McCaldin and Hornoi devised of the silicon planar process and Kilby and Noyce established an Integrated circuit (IC) that could
Robert_W._Bower
MOSFET technology node
multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology. Since at least 1997, process nodes have been named purely on a marketing
14_nm_process
Semiconductor manufacturing processes
Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). Sub-10-nm planar-bulk-CMOS devices using lateral junction control. IEEE International Electron
5_nm_process
Method for the manufacture of acetic acid
catalytic cycle for the Cativa process, shown above, begins with the reaction of methyl iodide with the square planar active catalyst species (1) to form
Cativa_process
Reflex of the human foot
pathological plantar reflex is the first and only indication of a serious disease process and a clearly abnormal plantar reflex often prompts detailed neurological
Plantar_reflex
Overview of and topical guide to information technology
Hybrid integrated circuit (HIC) Monolithic integrated circuit (IC) chip Planar process MOS integrated circuit (MOS IC) Silicon-gate technology (SGT) MOS IC
Outline of information technology
Outline_of_information_technology
Graph with at most one crossing per edge
In topological graph theory, a 1-planar graph is a graph that can be drawn in the Euclidean plane in such a way that each edge has at most one crossing
1-planar_graph
Technical award
advancing the theory, practice, and application of computer and information processing technology." Another award considered to be the "most prestigious technical
W._Wallace_McDowell_Award
Egyptian engineer (1924–2009)
MOSFET (MOS transistor) by Atalla and Dawon Kahng at Bell Labs, the planar process by Jean Hoerni at Fairchild Semiconductor. Building on his earlier pioneering
Mohamed_M._Atalla
20th-century English electronics engineer
microelectronics, a role he assigned to Robert Noyce and Jean Hoerni, whose planar process turned Kilby's initial prototype into a reliable manufacturable product
Geoffrey_Dummer
American mainframe and supercomputer firm (1957–1999)
selected the new silicon transistors that were developmed using the planar process. Manufactured by Fairchild Semiconductor,these silicon transistors were
Control_Data_Corporation
Mechanical linkage consisting of four links connected by joints in a loop
assembly is called a planar four-bar linkage. Spherical and spatial four-bar linkages also exist and are used in practice. Planar four-bar linkages are
Four-bar_linkage
759368. S2CID 1558618. Fountain, T J (September 1980). "Clip 4 parallel processing system" (PDF). IEEE Proceedings. 127 (5): 219–224. Retrieved 5 March 2025
Timeline of computing 1950–1979
Timeline_of_computing_1950–1979
Medical imaging technique
Resonance Imaging: A Signal Processing Perspective. Wiley. ISBN 978-0-7803-4723-6. Schmitt F, Stehling MK, Turner R (1998). Echo-Planar Imaging: Theory, Technique
Physics of magnetic resonance imaging
Physics_of_magnetic_resonance_imaging
Chemical reaction in which two ligands of a metal complex combine
Olefin Process which produces detergent precursors. Factors affecting the rate of olefin insertions include the formation of the cyclic, planar, four-center
Migratory_insertion
Topological quantum error correcting code
planar code. As of 2025, Google Quantum AI has implemented a distance-7 planar code on their newest generation of superconducting quantum processors,
Surface_code
Graph with edges non-crossing and upward
In graph drawing, an upward planar drawing of a directed acyclic graph is an embedding of the graph into the Euclidean plane, in which the edges are represented
Upward_planar_drawing
Object detection system using radio waves
Continuous-wave radar Doppler radar Fm-cw radar Monopulse radar Passive radar Planar array radar Pulse-doppler Synthetic-aperture radar Synthetically thinned
Radar
On tangency patterns of circles
planar. The circle packing theorem states that these are the only requirements for a graph to be a coin graph: every finite connected simple planar graph
Circle_packing_theorem
the most critical device component in integrated circuit (IC) chips. Planar process, developed by Jean Hoerni at Fairchild Semiconductor in early 1959,
List_of_MOSFET_applications
also plays a major role in other biological processes, such as wound healing and embryonic development. Planar cell polarity was first described in insects
Planar_cell_polarity
Concept in probability theory
conjectured scaling limit of the planar uniform spanning tree (UST) and the planar loop-erased random walk (LERW) probabilistic processes, and developed by him together
Schramm–Loewner_evolution
Representation of a graph's triconnected components
graph, and the connection between this decomposition and the planar embeddings of a planar graph, were first investigated by Saunders Mac Lane (1937);
SPQR_tree
On forbidden minors in planar graphs
forbidden graph characterization of planar graphs, named after Klaus Wagner, stating that a finite graph is planar if and only if its minors include neither
Wagner's_theorem
On graph drawing with integer edge lengths
every planar graph have an integral Fáry embedding? More unsolved problems in mathematics In mathematics, Harborth's conjecture states that every planar graph
Harborth's_conjecture
On coloring the edges of graphs
path of two adjacent edges. In Vizing's planar graph conjecture, Vizing (1965) states that all simple, planar graphs with maximum degree six or seven
Vizing's_theorem
Digital planar holography (DPH) is a method for designing and fabricating miniature components for integrated optics. It was invented by Vladimir Yankov
Digital_planar_holography
Israeli mathematician
original or more elegant than the original. Besides conformally invariant planar processes and SLE, he made fundamental contributions to several topics: The circle
Oded_Schramm
American digital display manufacturer
Planar Systems, Inc. is an American digital display manufacturing corporation with a facility in Hillsboro, Oregon. Founded in 1983 as a spin-off from
Planar_Systems
Polishing technique used during semiconductor fabrication
development of an additive patterning process, which relies on the unique abilities of CMP to remove material in a planar and uniform fashion and to stop repeatably
Chemical-mechanical_polishing
Classification of a two-dimensional repetitive pattern
three-dimensional space groups. A proof that there are only 17 distinct groups of such planar symmetries was first carried out by Evgraf Fedorov in 1891 and then derived
Wallpaper_group
Chemical element with atomic number 47 (Ag)
slightly more stable than those of copper(III). For instance, the square planar periodate [Ag(IO5OH)2]5− and tellurate [Ag{TeO4(OH)2}2]5− complexes may
Silver
Family of problems in computational geometry
some edges to a planar subdivision, in order to make all faces monotone, obtaining what is called a monotone subdivision. This process does not add any
Point_location
Photographic technique for capturing objects
as vases or ceramic vessels. The objective of this process is to present to the observer a planar representation of the object's characteristics, most
Rollout_photography
Planar graph embedding where edges map to straight-line segments
theory, a planar straight-line graph (PSLG), also called a straight-line plane graph or plane straight-line graph, is an embedding of a planar graph in
Planar_straight-line_graph
Month of 1959
Unity. Jean Hoerni filed a patent application (No. 3,064,167) for the planar process under the name "method of protecting exposed p-n junctions at the surface
May_1959
Planar fabric in rock
Cleavage, in structural geology and petrology, describes a type of planar rock feature that develops as a result of deformation and metamorphism. The degree
Cleavage_(geology)
Magic: The Gathering expansion block
expert-level block consisting of the expansion sets Time Spiral (October 6, 2006), Planar Chaos (February 2, 2007), and Future Sight (May 4, 2007). It is set on the
Time_Spiral
Method of predicting the bonding properties of certain organometallic compounds
are valid for most other geometries. The exception is square-planar because square-planar complexes typically abide by the 16-electron rule. Assuming ligands
Isolobal_principle
Set of laboratory techniques for separation of mixtures
with DNA, the higher the salt concentration needed to elute that protein. Planar chromatography is a separation technique in which the stationary phase is
Chromatography
Organic compound
O=C(−NH2)2. The urea molecule is planar when in a solid crystal because of sp2 hybridization of the N orbitals. It is non-planar with C2 symmetry when in the
Urea
Planar maps require at most five colors
color theorem was found only in 1976. First of all, one associates a simple planar graph G {\displaystyle G} to the given map, namely one puts a vertex in
Five_color_theorem
Tree data structure that partitions a 2D area
Alves, Sidiney G.; de Oliveira, Marcelo M. (2022). "Contact Process on Weighted Planar Stochastic Lattice". Journal of Statistical Mechanics (6): 063201
Quadtree
Technique of shooting liquid metal on cooled rotating drum
consistency. Planar Flow Casting (PFC) is a commonly used melt spinning process for the industrial fabrication of wide metallic glass sheets. In this process, the
Melt_spinning
Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). "Sub-10-nm planar-bulk-CMOS devices using lateral junction control". IEEE International Electron
List of semiconductor scale examples
List_of_semiconductor_scale_examples
Imaging Technology
A planar Fourier capture array (PFCA) is a tiny camera that requires no mirror, lens, focal length, or moving parts. It is composed of angle-sensitive
Planar_Fourier_capture_array
A Sawyer motor or planar motor (also called area drive) is a multi-coordinate drive that can perform several independent movements in one plane. Goods
Sawyer_motor
Fracture or discontinuity in displaced rock
In geology, a fault is a planar fracture or discontinuity in a volume of rock across which there has been significant displacement as a result of rock-mass
Fault_(geology)
Chemical element with atomic number 91 (Pa)
polymeric chain, all chlorine atoms lie in one graphite-like plane and form planar pentagons around the protactinium ions. The 7-coordination of protactinium
Protactinium
Any planar graph can be subdivided by removing a few vertices
In graph theory, the planar separator theorem is a form of isoperimetric inequality for planar graphs, that states that any planar graph can be split into
Planar_separator_theorem
1924), Swiss-American microelectronics engineer, developer of the planar process. January 15 – Kenneth V. Thimann (b. 1904), English-American plant physiologist
1997_in_science
Rigid structure that consists of two-force members only
as revolutes, as is necessary for the links to be two-force members. A planar truss is one where all members and nodes lie within a two-dimensional plane
Truss
PLANAR PROCESS
PLANAR PROCESS
Female
English
From the name of a Tolkien character, ELANOR means "star sun."
Boy/Male
Basque Hebrew
Help of God.
Surname or Lastname
French (Planté)
French (Planté) : topographic name for someone living by an area of planted ground, a herb garden, shrubbery, or more specifically a vineyard.English : variant of Plant.
Male
Russian
(Russian ЛаÌзарь, Serbian: Лазар): Russian and Serbian form of Latin Lazarus, LAZAR means "my God has helped."
Female
Turkish
Turkish name PINAR means "spring."
Girl/Female
Hindu
God
Surname or Lastname
German, Jewish (Ashkenazic), and Czech (Platnéř)
German, Jewish (Ashkenazic), and Czech (Platnéř) : occupational name for an armorer (see Blattner).English : occupational name for a plate maker, from a Middle English agent derivative of Old French platon ‘metal plate’. Compare Platten.
Male
Hindi/Indian
(पà¥à¤°à¤£à¤µ) Hindi name PRANAV means "Om," the sacred syllable.
Surname or Lastname
English and French
English and French : metonymic occupational name for a gardener, in particular someone with a herb garden, from Middle English plant (Old English plante), Old French plante ‘herb’, ‘shrub’, ‘young tree’. In English it may also be a nickname for a tender or delicate individual, from the same word in a transferred sense.French : topographic name for a planted area, in particular one planted with herbs or vines. Compare Plantier.Jewish (eastern Ashkenazic) : unexplained.
Surname or Lastname
English
English : from an agent derivative of Middle English pleyen ‘to play’, hence an occupational name for an actor or musician or a nickname for a successful competitor in contests of athletic or sporting prowess.
Male
Hebrew
(×ֶלְעָזָר) Hebrew name ELAZAR means "god has helped." In the bible, this is the name of several characters, including a high priest son of Aaron. In use by the Basques.
Surname or Lastname
English
English : probably a variant spelling of Player.
Male
Hindi/Indian
(पà¥à¤°à¤£à¤¯) Hindi name PRANAY means "romance."
Boy/Male
Indian, Tamil
Planner; Plan to do
Surname or Lastname
English
English : occupational name for a maker of plate-armor or armor-plates, from an agent derivative of Middle English plate ‘armor-plate’.English : from an agent derivative of Old French plait ‘plea’ or plaitier ‘to plead’, hence an occupational name or nickname for an advocate.
Boy/Male
Gaelic
Surname or Lastname
English (chiefly Berkshire)
English (chiefly Berkshire) : from Middle English planke ‘plank’ (Late Latin planca). It is not clear how this word was applied as a surname: it may be a topographic name for someone who lived near a plank bridge over a stream, a metonymic occupational name for a carpenter, or a nickname for a thin person.North German : nickname for a cantankerous person, from Middle Low German plank ‘quarrel’, ‘discord’.North German : metonymic occupational name from Middle Low German plank ‘measure for liquids’.South German : topographic name from Middle High German plank ‘plank’, ‘palisade’.South German : nickname for a fair-haired person, from a variant of Middle High German blanc ‘light’, ‘shining’.
Female
English
 English feminine form of Celtic Alan, possibly ALANA means "little rock."
Girl/Female
Israeli
Oak tree.
Female
Hebrew
(×Ö´×™×œÖ¸× Ö¸×”) Feminine form of Hebrew Ilan, ILANA means "tree."
PLANAR PROCESS
PLANAR PROCESS
Female
French
Feminine form of French Julien, JULIENNE means "descended from Jupiter (Jove)."
Girl/Female
Australian, British, English
Wisdom; Knowledge; Learning
Male
Arthurian
, ("warrior"); an enemy of king Arthur.
Boy/Male
Indian, Tamil
Sweet Person
Girl/Female
Indian
Pure, Clear, Tranquil, Serene
Boy/Male
Hindu
Girl/Female
English
Originally a diminutive used for names ending in -bina, like Albina, Columbina, and Robina, now...
Girl/Female
Norse
Frey's priestesses.
Boy/Male
Welsh
Chief.
Girl/Female
Gujarati, Indian, Punjabi, Sikh
Guru's Devotee; One who is Absorbed in the Guru
PLANAR PROCESS
PLANAR PROCESS
PLANAR PROCESS
PLANAR PROCESS
PLANAR PROCESS
n.
One who plans; a projector.
a.
Full; entire; complete; absolute; as, a plenary license; plenary authority.
n.
To furnish, or fit out, with plants; as, to plant a garden, an orchard, or a forest.
a.
Combining forms signifying flat, level, plane; as planifolious, planimetry, plano-concave.
a.
Of or pertaining to two planes.
v. t.
To post placards upon or within; as, to placard a wall, to placard the city.
n.
One who, or that which, planes; a planing machine; esp., a machine for planing wood or metals.
n.
A plank.
n.
One who owns or cultivates a plantation; as, a sugar planter; a coffee planter.
n.
The plane tree.
pl.
of Plaga
a.
Belonging to plants; as, plantal life.
v. t.
To make or cover with planks or boards; to plank.
imp. & p. p.
of Plane
n.
One who, or that which, plants or sows; as, a planterof corn; a machine planter.
a.
Eating, or subsisting on, plants; as, a plant-eating beetle.
v. t.
To cover or lay with planks; as, to plank a floor or a ship.
a.
Of or pertaining to the sole of the foot; as, the plantar arteries.
a.
Of or pertaining to a plane.