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Part of a machine instruction
processing unit), the opcodes are defined by the processor's instruction set architecture (ISA). They can be described using an opcode table. The types of operations
Opcode
Visual representation of all opcodes in an instruction set
An opcode table (also called an opcode matrix) is a visual representation of all opcodes in an instruction set. It is arranged such that each axis of
Opcode_table
Interpreted programming language
Variant Opcode Table". chip8.gulrak.net. "FX1E and VF · Issue #2 · Chromatophore/HP48-Superchip · GitHub". GitHub. CHIP-8 Variant Opcode Table an accurate
CHIP-8
Undocumented CPU instruction that has an effect
In computer science, an illegal opcode, also called an unimplemented operation, unintended opcode or undocumented instruction, is an instruction to a
Illegal_opcode
List of x86 microprocessor instructions
1996, order no. 94175-01, table 6-20, page 209 – uses the mnemonic OIO ("Official invalid opcode") for the 0F FF opcode. Intel, Software Developer's
List_of_x86_instructions
Instructions directly executable by a computer
possible through opcode-level programming to deliberately arrange the resulting code so that two code paths share a common fragment of opcode sequences. These
Machine_code
Model that describes the programmable interface of a computer processor
instructions. On the processing architecture, a given instruction may specify: opcode (the instruction to be performed) e.g. add, copy, test any explicit operands:
Instruction_set_architecture
Part of a computer instruction
an opcode prefix is a numeric prefix code that alters the function of a following opcode. On some instruction set architectures multiple opcode prefixes
Opcode_prefix
Machine instruction that indicates to a computer to do nothing
effects; for example, on the Motorola 68000 series of processors, the NOP opcode causes a synchronization of the pipeline. Listed below are the NOP instruction
NOP_(code)
Computer network protocol
and opcode ≠ 0. A fragmented message consists of one frame with FIN = 0 and opcode ≠ 0, followed by zero or more frames with FIN = 0 and opcode = 0,
WebSocket
Aspect of the instruction set architecture of CPUs
particular operand. Keeping the addressing mode specifier bits separate from the opcode operation bits produces an orthogonal instruction set. Even on a computer
Addressing_mode
32-bit RISC CPU architecture
differences. Each opcode (operation code) table is from User's Manual: Architecture (refer to external links.). 1st map opcodes All opcodes (operation codes)
V850
Type of computer instructions
sign-extension and points out the potential is much greater. Intel BCD opcodes Power ISA has a large range of bit manipulation instructions, largely due
Bit_manipulation_instructions
Instruction in computer program
addressing mode that should be used to locate the actual effective offset. This table lists the machine level branch or jump instructions found in several well-known
Branch_(computer_science)
Low-level programming language family
object code, the symbol table, the listing file, and the values of internal assembler parameters". Sometimes the term pseudo-opcode is reserved for directives
Assembly_language
Computer assembly language instruction
SIGTRAP. The opcode for INT3 is 0xCC, as opposed to the opcode for INT immediate8, which is 0xCD immediate8. Since the dedicated 0xCC opcode has some desired
INT_(x86_instruction)
or W=1. Opcode table The 10 fused-multiply-add operations and the 122 instruction variants they give rise to are given by the following table – with FMA4
List_of_x86_SIMD_instructions
Data structure in microprocessors
The interrupt descriptor table (IDT) is a data structure used by the x86 architecture to implement an interrupt vector table. The IDT is used by the processor
Interrupt_descriptor_table
Machine instruction executing another instruction repeatedly
repeat instructions (REP(∅/E/Z/NE/NZ)) which are called "repeat string opcode prefixes" and may only be applied to a small number of string instructions
Repeat_instruction
Method of transferring program control to another part of a program
In computer programming, a branch table or jump table is a method of transferring program control (branching) to another part of a program (or a different
Branch_table
has a single opcode. In others, some instructions have an opcode and one or more modifiers. E.g., on the IBM System/370, byte 0 is the opcode but when byte
Comparison of instruction set architectures
Comparison_of_instruction_set_architectures
Microprocessor instruction set
single byte opcodes (the "root instructions"), most of which are inherited from the 8080. The four remaining codes are used extensively as opcode prefixes:
Z80_instruction_set
Family of backward-compatible assembly languages
human-readable compared to raw machine code. Each machine code instruction is an opcode which, in assembly, is replaced with a mnemonic. Each mnemonic corresponds
X86_assembly_language
Type of program control instruction
jump table of pointers to code for handling the various cases implied by the data value. The data value could be added to the address of the table, with
Indirect_branch
16-bit microprocessor
used for debugging (as a breakpoint instruction), for creating indexed-opcode tables as used in byte-code interpreters and can also be used to perform a
TMS9900
8-bit microprocessor from 1975
instruction operation codes (opcodes) are 8 bits long and have the general form AAABBBCC, where AAA and CC define the opcode, and BBB defines the addressing
MOS_Technology_6502
Computer instruction executing another instruction
from a table of up to 255 instructions. Most instructions act as single instruction subroutines but branches are used to implement jump tables. Modern
Execute_instruction
of JMP (opcodes E9 and FF /4), CALL (opcodes E8 and FF /2), RET (opcodes C2 and C3), and the short/near forms of the Jcc instructions (opcodes 70..7F and
List of discontinued x86 instructions
List_of_discontinued_x86_instructions
Mechanism that ensures threads are not executed in parallel
import Lock INSTRUCTION_TABLE = { ... } def execute(bytecode: list) -> None: """Execute bytecode.""" lock = Lock() for (opcode, args) in bytecode: lock
Global_interpreter_lock
Visual programming language
Max Software and Ben Austin moved to Opcode Systems, which became the publisher of record for Max. Although Opcode launched its commercial version named
Max_(software)
Executable file format
attribute), the compiler can generate optimized code with a simple indirect call opcode. Modern operating systems use address space layout randomization (ASLR)
Portable_Executable
Design flaw in 1993-1997 Intel processors
reside on a page, and the remainder of the table on the following page. The handler for the undefined opcode exception is then the last descriptor on the
Pentium_F00F_bug
List of computer processor instructions
the memory operand, and 9-bit branch destinations. Later revisions added opcode bits, allowing additional address bits. They are accumulator machines, with
PIC_instruction_listings
8-bit microcontroller family
90 change the meaning of the opcode byte completely. Prefix 90 exchanges X and Y in the following instruction. In the table below, these variants are combined
STM8
Communications protocol for lighting control
the same on all Art-Net packets, while the green portion is variable. The opcode (given in little endian) tells the recipient this is a packet containing
Art-Net
Instruction encoding rule for the x86 instruction set
set. Opcodes in x86 are generally one-byte, though two-byte instructions and prefixes exist. ModR/M is a byte that, if required, follows the opcode and
ModR/M
Digital circuit
particular branch needs to be updated, it rewrites the opcode with the semantically equivalent opcode that hinted the proper history. This scheme obtains
Branch_predictor
1960s decimal computer
201–332. The 1401's instruction format is Opcode with [A-or-I-or-unit-address [B-address]] [modifier] word mark Opcodes are one character. Memory addresses
IBM_1401
Instruction for x86 microprocessors
In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from "CPU Identification")
CPUID
Data table used to control program flow
some redundancy, since the branch opcode and condition code mask are repeated alongside the branch offsets. Control tables containing only the offsets to
Control_table
Single chip microcontroller series by Intel
initial opcode byte, followed by up to 2 bytes of operands. 1⁄4 of the opcode bytes, x0–x3, are used for irregular opcodes. 3⁄4 of the opcode bytes, x4–xF
Intel_MCS-51
Source code that alters its instructions to the hardware while executing
switch { replace the opcode "increase" above with the opcode to decrease, or vice versa } } Note that two-state replacement of the opcode can be easily written
Self-modifying_code
Bug in the Intel P5 Pentium floating-point unit
directly patch the machine code of existing executables to replace the FDIV opcode with an illegal instruction. This would then trigger an exception that an
Pentium_FDIV_bug
Assembly language and bytecode for web browsers
concatenation of the SIMD prefix, plus an opcode that is valid after the SIMD prefix, forms each SIMD opcode. The SIMD opcodes bring an additional 236 instructions
WebAssembly
Comprehensive list of features of x86-based computers
structures, CMOS settings, memory and port addresses, as well as processor opcodes for x86 machines from the 1981 IBM PC up to 2000 (including many clones)
Ralf_Brown's_Interrupt_List
CMOS microprocessor in the 6502 family
addressing modes, produce a total of 151 opcodes of the possible 256 8-bit opcode patterns. The remaining 105 unused opcodes are undefined, with the set of codes
WDC_65C02
Family of instruction set architectures
produces the efficient add to AL opcode of 04h, whilst using the BL register produces the generic and longer add to register opcode of 80C3h. Another example
X86
Instruction for x86 processors
FCMOV is a floating point conditional move opcode of the Intel x86 architecture, first introduced in Pentium Pro processors. It copies the contents of
FCMOV
8-bit microprocessor
registers. The binary opcodes (machine language) were identical, but preceded by a new opcode prefix. Zilog published the opcodes and related mnemonics
Zilog_Z80
Processor executing one instruction in minimal clock cycles
conclusions worked in concert; removing instructions would allow the instruction opcodes to be shorter, freeing up bits in the instruction word which could then
Reduced instruction set computer
Reduced_instruction_set_computer
System to identify resources on a network
follows: QR: 1 bit Indicates if the message is a query (0) or a reply (1). OPCODE: 4 bits The type can be QUERY (standard query, 0), IQUERY (inverse query
Domain_Name_System
Microprocessor produced by Western Digital
ever produced. When a standard WD16 processor executes opcodes F500 to FFFF, the reserved opcode trap is taken, loading PC from 001A. The high-order ten
WD16
CLASS { &opcode INTEGER UNIQUE, &InvocationParsType, &ResponseParsAndResultType, &ExceptionList ERROR OPTIONAL } WITH SYNTAX { OPCODE &opcode REQUEST ARGUMENTS
Information Object Class (ASN.1)
Information_Object_Class_(ASN.1)
Instruction set architecture extension for microprocessors
operands. Like the VEX coding scheme, the EVEX prefix unifies existing opcode prefixes and escape codes, memory addressing and operand length modifiers
EVEX_prefix
Computer security exploit technique
"certain machine instructions which happen to contain the return opcode in their opcodes or immediate operands", such as movl $0xC3, %eax. The ARMv8.3-A
Return-oriented_programming
Parallel computing platform and programming model
cache per SM partition and 16 KiB L1 instruction cache per SM "asfermi Opcode". GitHub. for access with texture engine only 25% disabled on RTX 4060,
CUDA
Associates addresses in the layers of a networked device implementation
request or reply; the ARP standard specifies that the opcode is only processed after the ARP table has been updated from the address fields. Many operating
Address_Resolution_Protocol
Personal computer, invented in 1970
Opcode matrix for the Kenbak-1 instruction set High octal digits Low octal digit 0 1 2 3 4 5 6 7 00 HALT SFTR A1 SET 0 b0 XXX ADD A #XXX ADD A XXX ADD
Kenbak-1
Abstract machine that uses only one instruction
that uses only one instruction – obviating the need for a machine language opcode. With a judicious choice for the single instruction and given arbitrarily
One-instruction_set_computer
64-bit RISC instruction set architecture
It has a 6-bit opcode field, a 5-bit Ra field, a 5-bit Rb field and a 16-bit displacement field. Branch instructions have a 6-bit opcode field, a 5-bit
DEC_Alpha
8-bit microprocessor
the regular encoding of the MOV instruction (using a quarter of available opcode space), there are redundant codes to copy a register into itself (MOV B
Intel_8080
Software responsible for starting the computer
and LOADER support the 7.07 sectors had to resort to self-modifying code, opcode-level programming, controlled utilization of side effects, multi-level data/code
Bootloader
Fault initiated by x86 processors due to an access violation
classify some exceptions not related to access violations, such as illegal opcode exceptions, as general protection faults, even though they have nothing
General_protection_fault
1999 studio album by Static-X
of plywood and piezo microphones to record the kick, snare and toms into Opcode Vision. The cymbals were then played separately on top. Samples were programmed
Wisconsin_Death_Trip_(album)
Software that executes source code directly
particular code segment is executed the interpreter simply loads or jumps to the opcode mapping in the template and directly runs it on the hardware. Due to its
Interpreter_(computing)
Program whose source code consists entirely of calls to functions
complex. The decoding of single byte opcodes can be very simply and efficiently handled by a branch table using the opcode directly as an index. For instructions
Threaded_code
optional fields. The fifth and sixth field is optional (pink background in table) and appropriately named “options” and “option data”. Davison, Brian D.
Internet_Cache_Protocol
System routines for Classic Mac OS
Macintosh operating system executes system calls using that processor's illegal opcode exception handling mechanism. Motorola specified that instructions beginning
Macintosh_Toolbox
Firmware for hardware initialization and OS runtime services
interfaces, data structures, memory and port addresses, and processor opcodes for the x86 architecture System Management BIOS (SMBIOS) UEFI (Unified
BIOS
Open-source CPU instruction set architecture
compensate, RISC-V's 32-bit instructions are actually 30 bits; 3⁄4 of the opcode space is reserved for an optional (but recommended) variable-length compressed
RISC-V
Unit of data on an Ethernet network
and annex 31A. doi:10.1109/IEEESTD.2018.8457469. ISBN 978-1-5044-5090-4. Opcodes are transmitted high-order octet first. Within each octet, bits are transmitted
Ethernet_frame
Methods to calculate the day of the week
devices, there is similarly less need of either processor registers or opcodes, depending on the intended design objective. The tabular forerunner to
Determination of the day of the week
Determination_of_the_day_of_the_week
64-bit extension of the ARM architecture
after its introduction in ARMv8-A; it is not included in ARMv8-M. The main opcode for selecting which group an A64 instruction belongs to is at bits 25–28
AArch64
Programmable machine that processes data
code or opcode for short). The command to add two numbers together would have one opcode; the command to multiply them would have a different opcode, and
Computer
64-bit extension of x86 architecture
Intel 64. The 0F 0D /r opcode with the ModR/M byte's Mod field set to 11b is a Reserved-NOP on Intel 64 but will cause #UD (invalid-opcode exception) on AMD64
X86-64
Instruction set architecture developed by Digital Equipment Corporation
on the stack. The caller then adds the number of arguments to the MARK opcode and pushes that result on the stack. The value of SP is copied to R5. Finally
PDP-11_architecture
Atari 8-bit computer 6502 assembler
processing and conditional assembly. The cartridge version added 65C02 opcode support as well as a condensed version of Dunion's Debugging Tool (DDT)
MAC/65
Piece of software or hardware that creates and runs virtual machines
program includes a hypervisor-call handler that intercepts DIAG ("Diagnose", opcode x'83') instructions used within a virtual machine. This provides fast-path
Hypervisor
Discontinued Intel microprocessor architecture
is terminated by the 0 to 5 bit opcode, if any (some classes contain only one instruction and therefore have no opcode). "The Format field permits the
Intel_iAPX_432
Mainframe computer systems made by IBM through the 1950s and early 1960s
address. Sign (1 bit) – Whole-word (-) or Half-word (+) operand address Opcode (5 bits) – 32 instructions Address (12 bits) – 4096 Half-word addresses
IBM_700/7000_series
Computer of the Saturn V rocket
4-bit opcode field (least-significant bits) and a 9-bit operand address field (most-significant bits). This left it with sixteen possible opcode values
Launch Vehicle Digital Computer
Launch_Vehicle_Digital_Computer
Commands in some high-level programming languages
simplest, way to program in machine language was to use BASIC to POKE the opcode values into memory. Doing much low-level coding like this usually came from
PEEK_and_POKE
Instructional model of a computer
the mailbox with that number. Each instruction contains two fields: An opcode (indicating the operation to perform) and the address field (indicating
Little_Man_Computer
Programming language
multiple string parameters. Most oscillator opcodes will use an internal sine function table if the table number is omitted. Command-line options can
Csound
Family of block-oriented display terminals and printers made by IBM
headers. The following table includes datastream commands and CCW opcodes for local non-SNA controllers; it does not include CCW opcodes for local SNA controllers
IBM_3270
given virtual machine, each covering a different set of functions. The table here summarizes elements for which the virtual machine designs are intended
Comparison of application virtualization software
Comparison_of_application_virtualization_software
Instruction set designed to be run by a software interpreter
objects. The name bytecode stems from instruction sets that have one-byte opcodes followed by optional parameters. Intermediate representations such as bytecode
Bytecode
Process of starting a computer
and LOADER support the 7.07 sectors had to resort to self-modifying code, opcode-level programming in machine language, controlled utilization of (documented)
Booting
Early microprocessor
instructions, the upper four bits (the high-order nibble) specify the instruction opcode and are latched into the I register during instruction fetch. The lower
RCA_1802
System of digitally encoding numbers
The Intel 8080, the Zilog Z80 and the CPUs of the x86 family provide the opcode DAA (Decimal Adjust Accumulator on 8080 and Z80 / Decimal Adjust for Addition
Binary-coded_decimal
Computer file system architecture design
trying to determine a floppy disk's format should test on all mentioned opcode sequences at sector offset 0x000 in addition to looking for a valid media
Design_of_the_FAT_file_system
Component of the Blu-ray Disc digital rights management system
instruction filter is available that can perform an XOR operation on an opcode before executing it. By varying the instruction filter at runtime, the compiler
BD+
Microprocessor model
LTR, CLTS. There are also new exceptions (internal interrupts): invalid opcode, coprocessor not available, double fault, coprocessor segment overrun, stack
Intel_80286
8-bit microprocessor
regular encoding of the MOV instruction (using nearly a quarter of the entire opcode space) there are redundant codes to copy a register into itself (MOV B,B
Intel_8085
Input where a function output does not matter
normal operational state. Decision table Side effect Short-circuit evaluation Incomplete address decoding Incomplete opcode decoding Logic redundancy Undefined
Don't-care_term
Instructions for the x86 microprocessors
VEX coding scheme introduces a new set of code prefixes that extends the opcode space, allows instructions to have more than two operands, and allows SIMD
Advanced_Vector_Extensions
Microprocessor
68000 such as the Hitachi FD1089 and FD1094 store decryption keys for opcodes and opcode data in battery-backed memory. These were used in certain Sega arcade
Motorola_68000
Computer science topic
connective; some vendors use the term Boolean operation for 16 distinct opcodes. Here are the bitwise equivalent operations of two bits P and Q: The ternary
Bitwise_operation
position of the 2nd key itself (21 and 26) are never used as opcodes. Here is the table of the codes produced with the 2nd prefix: The Ind key allows
Keystroke_programming
Programming language and design system
The character @ is used to escape characters and to invoke raw Z-machine opcodes. The Inform system also contains the Inform library, which automates nearly
Inform
OPCODE TABLE
OPCODE TABLE
Boy/Male
Bengali, Celebrity, Gujarati, Hindu, Indian, Kannada, Kashmiri, Malayalam, Marathi, Punjabi, Sanskrit, Sikh, Sindhi, Tamil, Telugu
Indestructible; Legend; Immortal; Happy; Oppose Destruction; Long Life; Unconquerable
Surname or Lastname
English (of Norman origin)
English (of Norman origin) : occupational name denoting a servant who carried the ewer to guests at table so that they could wash their hands, Anglo-Norman French and Middle English ewerer (related to ewere ‘jug’), with the French definite article l’.Cornish : variant of Flower 4.
Surname or Lastname
English
English : nickname from Middle English pode ‘toad’.
Girl/Female
Biblical
Cultivated field or table-land.
Boy/Male
British, English
From the Upper Forest
Surname or Lastname
English
English : metonymic occupational name for a producer or seller of table linen, from Old French nappe ‘table cloth’.English : either a variant spelling of Knapp or a reduced variant of Scottish McNabb.Altered spelling of German Knapp.German : metonymic occupational name for a bowl and cup maker, from Middle Low German nap ‘bowl’, ‘mug’, or alternatively, from an old personal name formed with an element cognate with Old High German (gi-)nÄda ‘grace’, ‘benevolence’.
Female
Japanese
(1-儀, 2-典, 3-則, 4-法) Japanese unisex name NORI means 1) "ceremony, regalia," 2) "code, precedent," 3) "model, rule, standard," 4) "law, rule."
Girl/Female
Hindu
Code
Boy/Male
Muslim
Table companion. Associate.
Surname or Lastname
English
English : from Old English bord ‘board’, ‘plank’, ‘table’, hence a metonymic occupational name for a carpenter or a topographic name for someone who lived in a plank-built cottage.
Surname or Lastname
English (West Midlands)
English (West Midlands) : habitational name of uncertain origin: probably from a lost settlement called Buddeley in Tabley Superior, Cheshire. Another possibility is Budleigh in Devon (Bodelie in Domesday Book), named with Old English budda ‘beetle’ (or the same word used as a byname) + lēah ‘woodland clearing’.
Girl/Female
Tamil
Code
Surname or Lastname
Welsh
Welsh : Anglicized form of Welsh ap Rhiddid ‘son of Rhiddid’, a personal name of unexplained etymology.Welsh : Anglicized form of ap Redith ‘son of Redith’, a short form of Meredith; the short form occurs only in this Anglicized spelling.Welsh : from the personal name Predyr, Peredur (perhaps from Old Welsh peri ‘spears’ + dur ‘hard’, ‘steel’), which was borne, in Arthurian legend, by one of the knights of the Round Table.Welsh : occupational name, from Welsh prydydd ‘bard’.English : habitational name from Priddy in Somerset, named probably with Celtic words meaning ‘earth house’.
Surname or Lastname
English (of Norman origin)
English (of Norman origin) : occupational name from Old French tablier ‘joiner’.
Surname or Lastname
English
English : variant spelling of Coad.
Surname or Lastname
German, Dutch, and Jewish (Ashkenazic)
German, Dutch, and Jewish (Ashkenazic) : from Middle High German or Middle Low German banc, or Yiddish bank ‘bench’, ‘table’, ‘counter’, in any of various senses, e.g. a metonymic occupational name for anyone whose work required a bench or counter, for example a butcher, baker, court official, or money changer.Danish and Swedish : topographic name from bank ‘(sand)bank’ or a habitational name from a farm named with this word.Danish and Swedish : from bank ‘noise’, hence a nickname for a loud or noisy person. Compare Bang.Danish : habitational name from the German place name Bänkau.English : probably a variant of Banks.Americanized spelling of Polish Bąk, literally ‘horsefly’; perhaps a nickname for an irritating person.Hungarian (Bánk) : from a pet form of the old secular personal name Bán.
Surname or Lastname
English
English : nickname for a person who insisted on a strict code of social behavior.German : topographic name for someone who lived on or by a hill, from Middle High German stickel ‘hill’, ‘slope’ + the suffix -er denoting an inhabitant; in the south an occupational name for someone who shapes and sets stakes in vineyards.
Surname or Lastname
English
English : from Middle English chike ‘young fowl’ (a shortened form of chiken), applied as a metonymic occupational name for someone who bred poultry for the table, or as a nickname from the same word used as a term of endearment.English : variant of Cheek.
Boy/Male
Biblical
A moist table.
Surname or Lastname
Welsh
Welsh : Anglicized form of the Welsh patronymic ap Heilyn ‘son of Heilyn’, which is probably a derivative of a word meaning ‘to serve at table’.English : habitational name from Palling in Norfolk or Poling in Sussex. These were named in Old English with the personal names Pælli and PÄl respectively, + -ingas ‘followers of’, ‘dependants of’.French : unexplained.A Palin, also written Palen and Pallin, from the Poitou region of France, is documented in Quebec City in 1692, with the secondary surname Dabonville.
OPCODE TABLE
OPCODE TABLE
Boy/Male
Tamil
Girl/Female
Teutonic American
Oath.
Male
Czechoslovakian
, man of God, or, hero of god.
Male
Hindi/Indian
Bengali form of Hindi Vasant, BASANT means "spring."
Boy/Male
Arabic, Muslim
One of the Ninety-nine Names of God; Wisdom
Boy/Male
Hindu, Indian
Inspiration of Original Man
Boy/Male
Hindu, Indian
Guru
Male
Czechoslovakian
, farmer, husbandman.
Girl/Female
British, Danish, English, French, German, Latin
Violet; Purple; Violet Flower
Girl/Female
Gujarati, Hindu, Indian, Kannada, Marathi, Sanskrit, Tamil
Poetry in Motion
OPCODE TABLE
OPCODE TABLE
OPCODE TABLE
OPCODE TABLE
OPCODE TABLE
v. t.
To oppose.
v. t.
To oppose; to fight against.
n.
To place in front of, or over against; to set opposite; to exhibit.
n.
To resist or antagonize by physical means, or by arguments, etc.; to contend against; to confront; to resist; to withstand; as, to oppose the king in battle; to oppose a bill in Congress.
v. t.
To cross; to oppose.
n.
Any system of rules or regulations relating to one subject; as, the medical code, a system of rules for the regulation of the professional conduct of physicians; the naval code, a system of rules for making communications at sea means of signals.
v. i.
To make objection or opposition in controversy.
v. t.
To set against; to oppose.
imp. & p. p.
of Oppose
n.
To put in opposition, with a view to counterbalance or countervail; to set against; to offer antagonistically.
pl.
of Apode
n.
The after song; the part of a lyric ode which follows the strophe and antistrophe, -- the ancient ode being divided into strophe, antistrophe, and epode.
pl.
of Apode
p. pr. & vb. n.
of Oppose
v. i.
To act adversely or in opposition; -- with against or to; as, a servant opposed against the act.
v. t.
To oppose again.
n.
To compete with; to strive against; as, to oppose a rival for a prize.
v. i.
To be set opposite.
v. t.
To oppose; to resist.
v. i.
To oppose.