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Part of a machine instruction
In computing, an opcode (abbreviated from operation code) is an enumerated value that specifies the operation to be performed. Opcodes are employed in
Opcode
Visual representation of all opcodes in an instruction set
An opcode table (also called an opcode matrix) is a visual representation of all opcodes in an instruction set. It is arranged such that each axis of
Opcode_table
Instructions directly executable by a computer
possible through opcode-level programming to deliberately arrange the resulting code so that two code paths share a common fragment of opcode sequences. These
Machine_code
Undocumented CPU instruction that has an effect
In computer science, an illegal opcode, also called an unimplemented operation, unintended opcode or undocumented instruction, is an instruction to a
Illegal_opcode
American music software company
Opcode Systems, Inc. was an American music software company founded in 1985 by Dave Oppenheim and based in and around Palo Alto, California, USA. Opcode
Opcode_Systems
Low-level programming language family
Assembly language uses mnemonics to represent low-level machine instructions (opcodes), directives, and usually architectural registers and flags. Some of the
Assembly_language
Part of a computer instruction
an opcode prefix is a numeric prefix code that alters the function of a following opcode. On some instruction set architectures multiple opcode prefixes
Opcode_prefix
List of x86 microprocessor instructions
(6 bits for opcode C1 if it is encoded with a 64-bit operand-size under x86-64) On 80186 and later, sub-opcode /6 for the shift-opcodes C0/C1/D0/D1/D2/D3
List_of_x86_instructions
Computer assembly language instruction
SIGTRAP. The opcode for INT3 is 0xCC, as opposed to the opcode for INT immediate8, which is 0xCD immediate8. Since the dedicated 0xCC opcode has some desired
INT_(x86_instruction)
Set of x86 processor instructions
The Intel BCD opcodes are a set of six x86 instructions that operate with binary-coded decimal numbers: AAA, DAA, AAS, DAS, AAM, and AAD. Most arithmetic
Intel_BCD_opcodes
Programmable machine that processes data
code or opcode for short). The command to add two numbers together would have one opcode; the command to multiply them would have a different opcode, and
Computer
Combinational digital circuit
called operands, and a code indicating the operation to be performed (opcode); the ALU's output is the result of the performed operation. In many designs
Arithmetic_logic_unit
Computer security testing tool
against a remote target machine. Other important sub-projects include the Opcode Database, shellcode archive and related research. The Metasploit Project
Metasploit
Computer network protocol
and opcode ≠ 0. A fragmented message consists of one frame with FIN = 0 and opcode ≠ 0, followed by zero or more frames with FIN = 0 and opcode = 0,
WebSocket
Interpreted programming language
the semantics of a few of the opcodes, and SCHIP continued to use those new semantics in addition to changing other opcodes. Many online resources about
CHIP-8
Computer machine code instruction
design flaw was discovered by programmers. Due to incomplete opcode decoding, two illegal opcodes, 0x9D and 0xDD, will cause the program counter on the processor
Halt and Catch Fire (computing)
Halt_and_Catch_Fire_(computing)
Single chip microcontroller series by Intel
initial opcode byte, followed by up to 2 bytes of operands. 1⁄4 of the opcode bytes, x0–x3, are used for irregular opcodes. 3⁄4 of the opcode bytes, x4–xF
Intel_MCS-51
8-bit microprocessor
registers. The binary opcodes (machine language) were identical, but preceded by a new opcode prefix. Zilog published the opcodes and related mnemonics
Zilog_Z80
Protocol
assigned by the program that generates any kind of query. QR - Query/Response. OPCODE - A 4-bit field that specifies the kind of query in this message. This value
Link-Local Multicast Name Resolution
Link-Local_Multicast_Name_Resolution
Instruction set architecture
(immediate), and J (jump). Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a shift amount
MIPS_architecture
Microprocessor instruction set
single byte opcodes (the "root instructions"), most of which are inherited from the 8080. The four remaining codes are used extensively as opcode prefixes:
Z80_instruction_set
Basic instruction cycle in a computer
operations based on specific opcodes in the instruction. For example, in RISC-V architecture, funct3 and funct7 opcodes exist to distinguish whether an
Instruction_cycle
Machine instruction that indicates to a computer to do nothing
effects; for example, on the Motorola 68000 series of processors, the NOP opcode causes a synchronization of the pipeline. Listed below are the NOP instruction
NOP_(code)
8-bit microprocessor from 1975
instruction operation codes (opcodes) are 8 bits long and have the general form AAABBBCC, where AAA and CC define the opcode, and BBB defines the addressing
MOS_Technology_6502
Model that describes the programmable interface of a computer processor
instructions. On the processing architecture, a given instruction may specify: opcode (the instruction to be performed) e.g. add, copy, test any explicit operands:
Instruction_set_architecture
36-bit computer by Digital (1966–1983)
general instructions, the leftmost 9 bits, 0 to 8, contain an instruction opcode. Many of the possible 512 codes are not defined in the base model machines
PDP-10
Microprocessor produced by Western Digital
ever produced. When a standard WD16 processor executes opcodes F500 to FFFF, the reserved opcode trap is taken, loading PC from 001A. The high-order ten
WD16
64-bit RISC instruction set architecture
It has a 6-bit opcode field, a 5-bit Ra field, a 5-bit Rb field and a 16-bit displacement field. Branch instructions have a 6-bit opcode field, a 5-bit
DEC_Alpha
Aspect of the instruction set architecture of CPUs
particular operand. Keeping the addressing mode specifier bits separate from the opcode operation bits produces an orthogonal instruction set. Even on a computer
Addressing_mode
Communications protocol for lighting control
the same on all Art-Net packets, while the green portion is variable. The opcode (given in little endian) tells the recipient this is a packet containing
Art-Net
CPU optimization unit
Fetching the instruction opcodes from program memory well in advance is known as prefetching and it is served by using a prefetch input queue (PIQ). The
Prefetch_input_queue
Instruction set architecture extension for microprocessors
high-order bits set to four, which replaces sixteen opcodes numbered 0x40–0x4F. Previously, those opcodes were individual INC and DEC instructions for the
REX_prefix
Type of computer instructions
sign-extension and points out the potential is much greater. Intel BCD opcodes Power ISA has a large range of bit manipulation instructions, largely due
Bit_manipulation_instructions
has a single opcode. In others, some instructions have an opcode and one or more modifiers. E.g., on the IBM System/370, byte 0 is the opcode but when byte
Comparison of instruction set architectures
Comparison_of_instruction_set_architectures
Anomaly in computer security and programming
The Metasploit Project, for example, maintains a database of suitable opcodes, though it lists only those found in the Windows operating system. A buffer
Buffer_overflow
Series of 16-bit computers by Texas Instruments
of program SVC DATA >0000 R3 - Open I/O opcode DATA >0B00 R4 - Write I/O opcode DATA >0100 R5 - Close I/O opcode DATA STRING R6 - Message address DATA STRLEN
TI-990
Instruction for x86 processors
flags are set to 0, while AF flag is undefined. There are 9 different opcodes for the TEST instruction depending on the type and size of the operands
TEST_(x86_instruction)
Electronic test instrument that measures multiple signals from a circuit
timing diagrams, protocol decodes, state machine traces, opcodes, or may correlate opcodes with source-level software. Logic analyzers have advanced
Logic_analyzer
Processor executing one instruction in minimal clock cycles
conclusions worked in concert; removing instructions would allow the instruction opcodes to be shorter, freeing up bits in the instruction word which could then
Reduced instruction set computer
Reduced_instruction_set_computer
Central processing unit
the undocumented Z80 instructions were made official, including all the opcodes for instructions dealing with IX and IY as 8-bit registers (IXH, IXL, IYH
R800
Assembly language and bytecode for web browsers
concatenation of the SIMD prefix, plus an opcode that is valid after the SIMD prefix, forms each SIMD opcode. The SIMD opcodes bring an additional 236 instructions
WebAssembly
performed by these opcodes is the same for Intel and AMD. This documentation difference applies only to the MMX/SSE forms of these opcodes — for VEX/EVEX-encoded
List_of_x86_SIMD_instructions
1964 British computer specification
format: FF [Q] nnn m FF, the "order number", was the numerical instruction opcode. Q indicated the query function, and nnn and m were three-digit and one-digit
City_&_Guilds_Mnemonic_Code
Family of backward-compatible assembly languages
human-readable compared to raw machine code. Each machine code instruction is an opcode which, in assembly, is replaced with a mnemonic. Each mnemonic corresponds
X86_assembly_language
64-bit x86 register
In x86-64 mode, RDTSC also clears the upper 32 bits of RAX and RDX. Its opcode is 0F 31. Pentium competitors such as the Cyrix 6x86 did not always have
Time_Stamp_Counter
Type of program control instruction
Machine code General concepts Instruction set Opcode Illegal opcode Opcode table Opcode prefix Operand Addressing mode Instructions NOP Branch Indirect
Indirect_branch
Assembly languages for the RISC-V computer architecture
with one or more operands to translate into one or more bytes known as an opcode. RISC-V processors feature a set of registers that serve as storage for
RISC-V_assembly_language
Instruction set architecture developed by Digital Equipment Corporation
as defined above. This group of instructions takes up 75% of available opcodes. The ADD and SUB instructions use word addressing, and have no byte-oriented
PDP-11_architecture
Esoteric programming language
carriage returns. The language uses 10 opcodes and each word in the source code is translated into an opcode by adding all the digits in the word together
Leet_(programming_language)
Instruction for x86 processors
FCMOV is a floating point conditional move opcode of the Intel x86 architecture, first introduced in Pentium Pro processors. It copies the contents of
FCMOV
Data transfer protocol designed for mobile devices
Opcode Operation Name Explanation 0x9805 GetObjectPropList Metadata transfer 0x9806 SetObjectPropList 0x1019 MoveObject Rename a file or directory 0x101B
Media_Transfer_Protocol
Instruction set architecture extension for microprocessors
previously existing instruction codes. This serves the following purposes: The opcode map is extended to make space for future instructions. It allows instruction
VEX_prefix
Instruction in computer program
Machine code General concepts Instruction set Opcode Illegal opcode Opcode table Opcode prefix Operand Addressing mode Instructions NOP Branch Indirect
Branch_(computer_science)
Computer network protocol
request or response header containing an opcode that determines the associated operation, any relevant opcode-specific information (such as which ports
Port_Control_Protocol
Machine instruction executing another instruction repeatedly
repeat instructions (REP(∅/E/Z/NE/NZ)) which are called "repeat string opcode prefixes" and may only be applied to a small number of string instructions
Repeat_instruction
Computer instruction executing another instruction
Machine code General concepts Instruction set Opcode Illegal opcode Opcode table Opcode prefix Operand Addressing mode Instructions NOP Branch Indirect
Execute_instruction
instructions in the instruction set of the Common Intermediate Language bytecode. Opcode abbreviated from operation code is the portion of a machine language instruction
List_of_CIL_instructions
Abstract machine that uses only one instruction
that uses only one instruction – obviating the need for a machine language opcode. With a judicious choice for the single instruction and given arbitrarily
One-instruction_set_computer
Scripting language created in 1994
engine's internal format by using an opcode cache, which works by caching the compiled form of a PHP script (opcodes) in shared memory to avoid the overhead
PHP
Instruction for x86 microprocessors
In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from "CPU Identification")
CPUID
8-bit microcontroller family
rarely used branch instructions have had their opcodes changed to require a 90 prefix, and the unprefixed opcodes reassigned to signed branches which depend
STM8
CPU register that is always zero
benefit on performance. Some architectures accomplish this with dedicated opcodes, specialized variations of their basic instructions. Implementing these
Zero_register
of JMP (opcodes E9 and FF /4), CALL (opcodes E8 and FF /2), RET (opcodes C2 and C3), and the short/near forms of the Jcc instructions (opcodes 70..7F and
List of discontinued x86 instructions
List_of_discontinued_x86_instructions
Digital circuit
prediction by using 4 semantically equivalent branch opcodes to represent each branch operator type. The opcode used indicated the history of that particular
Branch_predictor
Process virtual machine developed by Meta
Zend Engine transforms PHP source code into opcodes that serve as a form of bytecode, and executes the opcodes directly on the Zend Engine's virtual CPU
HHVM
8-bit microcontroller product lines from STMicroelectronics
addressing modes (X) and (Y). The instruction set consists of one byte of opcode, followed by up to two one-byte operands. The instruction set can be summarized
ST6_and_ST7
Feature of HDMI
is acknowledged, the device tries another address. The second byte is an opcode which specifies the operation to be performed, and the number and meaning
Consumer_Electronics_Control
2013, a beta version of APCu (APC User Cache) is available, in which all opcode caching abilities have been removed to support user caches in shared memory
List_of_PHP_accelerators
Type of computer memory
CID0–2 H V Column C3–10 V AP V CID3 Vref CA L H H L L L Opcode OP0-6 L V Vref CS L H H L L L Opcode OP0-6 H V Refresh management L H H L L H CID3 Bank V
DDR5_SDRAM
8-bit microprocessor
were based on the same core as the 6502, and are opcode compatible, including undocumented opcodes. The parallel port was provided by using several formerly
MOS_Technology_6510
System to identify resources on a network
follows: QR: 1 bit Indicates if the message is a query (0) or a reply (1). OPCODE: 4 bits The type can be QUERY (standard query, 0), IQUERY (inverse query
Domain_Name_System
8-bit microprocessor
the regular encoding of the MOV instruction (using a quarter of available opcode space), there are redundant codes to copy a register into itself (MOV B
Intel_8080
Type of random-access memory
Description Bit Description ↓ RQ11 0 0 COL opcode 0 COLX opcode 0 ROWP opcode 0 ROWA opcode 1 COLM opcode ↓ RQ10 0 0 0 0 1 M3 Write mask low bits ↓ RQ9
XDR_DRAM
Instruction encoding rule for the x86 instruction set
set. Opcodes in x86 are generally one-byte, though two-byte instructions and prefixes exist. ModR/M is a byte that, if required, follows the opcode and
ModR/M
Family of instruction set architectures
formats for medium immediate instructions with length of 32-bit. Typical opcode length is 4 bits (bits 9–12 of most encoding types. Basic encoding formats
CompactRISC
Free and open-source virtual private network software
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 Opcode KeyID Session ID 4 32 Session ID 8 64 Session ID HMAC 12 96 HMAC ⋮ ⋮ 24
OpenVPN
8-bit microprocessor
most assemblers of the era mapped much more directly onto the low-level opcodes of the processor and lacked higher-level features. The MAC-8 was followed
BELLMAC-8
Associates addresses in the layers of a networked device implementation
announcement may be either request or reply; the ARP standard specifies that the opcode is only processed after the ARP table has been updated from the address
Address_Resolution_Protocol
1960s decimal computer
201–332. The 1401's instruction format is Opcode with [A-or-I-or-unit-address [B-address]] [modifier] word mark Opcodes are one character. Memory addresses
IBM_1401
Type of computer
code (sometimes called p-code), instructions will frequently have only an opcode commanding an operation, with no additional fields identifying a constant
Stack_machine
Mainframe computer, 1960s
the IBM 709: A three-bit opcode (prefix), 15-bit decrement (D), three-bit tag (T), and 15-bit address (Y) A twelve-bit opcode, two-bit flag (F), four unused
IBM_7090
programming language. Most PHP accelerators work by caching the compiled opcode/bytecode of PHP representation of php files to avoid the overhead of parsing
PHP_accelerator
Mechanism that ensures threads are not executed in parallel
"""Execute bytecode.""" lock = Lock() for (opcode, args) in bytecode: lock.acquire() INSTRUCTION_TABLE[opcode](args) lock.release() Free-Threaded Build
Global_interpreter_lock
Macintosh multimedia software
Open Music System (OMS) was a virtual studio management application by Opcode for the Classic Mac OS. Similar to FreeMIDI by Mark of the Unicorn and Audio
Open_Music_System
Software that executes source code directly
particular code segment is executed the interpreter simply loads or jumps to the opcode mapping in the template and directly runs it on the hardware. Due to its
Interpreter_(computing)
Graphics file format
version 2. This version featured 16-bit opcodes and numerous changes which enhanced its utility. PICT 1 opcodes were supported as a subset for backward
PICT
Computer memory used for small quantities of data
serial protocol consists of three phases: the opcode phase, address phase, and data phase. The opcode is usually the first 8 bits input to the serial
EEPROM
List of computer processor instructions
the memory operand, and 9-bit branch destinations. Later revisions added opcode bits, allowing additional address bits. They are accumulator machines, with
PIC_instruction_listings
8-bit microprocessor
Instructions are one to three bytes long. The instruction format is an opcode byte, followed by up to two bytes of operands. Operands can be an address
Intel_8008
Olivetti programmable calculator launched in 1964
Instruction Opcode Operation Sum + A = A + Chosen Register (hereinafter "CR") Subtraction - A = A - CR Multiplication x A = A * CR Division : A = A : CR
Programma_101
Instruction set designed to be run by a software interpreter
objects. The name bytecode stems from instruction sets that have one-byte opcodes followed by optional parameters. Intermediate representations such as bytecode
Bytecode
Serial bus connecting MAC devices with the Ethernet physical layer
always contains the combination '01'. OP The Opcode consists of 2 bits. There are two possible opcodes, read '10' or write '01'. PA5 5 bits, PHY address
Management_Data_Input/Output
CMOS microprocessor in the 6502 family
addressing modes, produce a total of 151 opcodes of the possible 256 8-bit opcode patterns. The remaining 105 unused opcodes are undefined, with the set of codes
WDC_65C02
1984 video game
Opcode Mnemonic Argument(s) Action 0 DAT B A non-executable instruction used to store the data value B. 1 MOV A, B Move the contents of A to location B
Core_War
Computer instruction which pauses execution
instruction is run in the "System Idle Process". On x86 processors, the opcode of HLT is 0xF4. On ARM processors, the similar instructions are WFI (Wait
HLT_(x86_instruction)
Network administration command-line tool
example.com any ;; global options: +cmd ;; Got answer: ;; ->>HEADER<<- opcode: QUERY, status: NOERROR, id: 4016 ;; flags: qr rd ra; QUERY: 1, ANSWER:
Dig_(command)
Floating-point microprocessor
three bits of the floating-point opcode. Then two "m" bits, then the latter half three bits of the floating-point opcode, followed by three "r" bits. The
Intel_8087
Design flaw in 1993-1997 Intel processors
compare and exchange of 8 bytes in register EAX). The bug also applies to opcodes ending in C9 through CF, which specify register operands other than EAX
Pentium_F00F_bug
Affix which is placed before the stem of a word
List of Greek and Latin roots in English Substring#Prefix Metric prefix Opcode prefix Wilson 2011, p. 152–153. sfn error: no target: CITEREFWilson2011
Prefix
Family of instruction set architectures
encoding space, most registers are expressed in opcodes using three or four bits, the latter via an opcode prefix in 64-bit mode, while at most one operand
X86
travel, tourism, insurance
OPCODE
OPCODE
OPCODE
OPCODE
OPCODE
OPCODE
OPCODE
OPCODE
OPCODE
travel, tourism, insurance