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Data structure
in a table of interrupt vectors. Each entry of the interrupt vector table, called an interrupt vector, is the address of an interrupt handler (also known
Interrupt_vector_table
Data structure in microprocessors
The interrupt descriptor table (IDT) is a data structure used by the x86 architecture to implement an interrupt vector table. The IDT is used by the processor
Interrupt_descriptor_table
Processing technique in computer science
science, a vectored interrupt is a processing technique in which the interrupting device directs the processor to the appropriate interrupt service routine
Vectored_interrupt
Computer assembly language instruction
are pushed, and the interrupt number is multiplied by four to index a new execution address which is loaded from the vector table. It is entirely possible
INT_(x86_instruction)
Low level firmware interface to the hardware
looking it up in a table of ISR starting-point addresses (called "interrupt vectors") in memory: the Interrupt vector table (IVT). An interrupt is invoked by
BIOS_interrupt_call
Comprehensive list of features of x86-based computers
the 1988-01-30 version (73728 bytes) of the interrupt list.) Szőr, Péter (2005-02-03). "Interrupt Vector Table". The Art of Computer Virus Research and Defense
Ralf_Brown's_Interrupt_List
Computer systems programming special block code
needed] Interrupt vector table Advanced Programmable Interrupt Controller (APIC) Inter-processor interrupt (IPI) Interrupt latency Interrupts in 65xx
Interrupt_handler
Signal to a computer processor emitted by hardware or software
distinct interrupt routine for each type of interrupt (or for each interrupt source), often implemented as one or more interrupt vector tables. To mask
Interrupt
Software that manages computer hardware resources
placed in a system table.) Read the integer from the data bus. The integer is an offset to the interrupt vector table. The vector table's instructions will
Operating_system
Topics referred to by the same term
IVT may refer to: Interrupt vector table, a memory construct in some processors Intel Virtualization Technology, a computer processor feature to simplify
IVT
16-bit microprocessor
8-bit interrupt number from the bus. This number is multiplied by four to point to the associated interrupt service routine address in the vector table. Maskable
Intel_8086
Microprocessor
"exception table" (interrupt vector table interrupt vector addresses) is fixed at addresses 0 through 1023, permitting 256 32-bit vectors. The first vector (RESET)
Motorola_68000
Computer virus
is booted from an infected sector, Form goes resident, hooks the interrupt vector table, and runs the original boot sector which it has hidden in an area
Form_(computer_virus)
Firmware for hardware initialization and OS runtime services
below address 0x00400 contains the interrupt vector table. BIOS POST has initialized the system timers, interrupt controller(s), DMA controller(s), and
BIOS
Programming language construct for special conditions
identically to an interrupt: the processor halts execution of the current program, looks up the interrupt handler in the interrupt vector table for that exception
Exception_handling
Operating mode of all x86-compatible CPUs
starting at address 0, is the permanent, immovable location of the interrupt vector table.) So, the actual amount of memory addressable by the 80286 and later
Real_mode
Memory page starting at address zero
space for the interrupt vector table (IVT) if they run in real mode. A similar technique of using the zero page for hardware related vectors was employed
Zero_page
Techniques to alter a program
on systems using the shared library concept, the interrupt vector table or the import descriptor table can be modified in memory. Essentially these tactics
Hooking
The interrupt disable flag is set in the status register. 65C816/65C802: PB is loaded with $00. PC is loaded from the relevant vector (see tables). The
Interrupts_in_65xx_processors
Family of computer interrupt controllers
between LAPICs. A single LAPIC may support up to 224 usable interrupt vectors from an I/O APIC. Vector numbers 0 to 31, out of 0 to 255, are reserved for exception
Advanced Programmable Interrupt Controller
Advanced_Programmable_Interrupt_Controller
Address from which a CPU starts fetching instructions after a reset
reset. The reset vector for 68000 processor family is 0x00000000 for Initial Interrupt Stack Register (IISR; Not really a reset vector and is used to initialize
Reset_vector
Computer program that returns control to a non-multitasking OS without exiting
that had previously altered the same interrupt vector. Cascade with other TSRs by calling the old interrupt vector. This can be done before or after they
Terminate-and-stay-resident program
Terminate-and-stay-resident_program
List of x86 microprocessor instructions
SENDUIPI is an index to pick an entry from the UITT (User-Interrupt Target Table, a table specified by the new UINTR_TT and UINT_MISC MSRs.) On Sapphire
List_of_x86_instructions
Structure on x86-based computers that holds information about a task
the Interrupt Stack Table (IST), which also resides in the TSS and contains logical (segment+offset) stack pointers. If an interrupt descriptor table specifies
Task_state_segment
at address 0000:7C00h. Upon execution, the virus intercepts the interrupt vector table by redirecting INT D3h, a seldom-used handler reserved for the IBM
AntiEXE
Signal in the system bus of an x86-based computer system
bytes of the interrupt service routine entry point reserved for INT 30h and the first byte of INT 31h in the x86 real mode interrupt vector table). However
A20_line
Laptop computer released by Epson in 1981
equivalent to the BIOS in modern PCs. ROM #0 also contains the interrupt vector table at FFF0-FFFF. FFFE-FFFF determines what the program counter should
Epson_HX-20
Paradigm used to simplify the design of hardware and software devices
section that starts up the modules. Other well-known examples are the interrupt vector table and the main loop. Some functions inherently have mixed semantics
Functional_design
Computer display standard for the Tandy 1000 series
first 128 KB of the address space. The first bank overlaps the interrupt vector table of the x86 CPU and the data area used by the BIOS, so it is generally
Tandy_Graphics_Adapter
BIOS interrupt call for disk access
interrupt call 13hex, the 20th interrupt vector in an x86-based (IBM PC-descended) computer system. The BIOS typically sets up a real mode interrupt handler
INT_13H
Microprocessor produced by Western Digital
a four-bit interrupt number provided by the interrupting device. The interrupt vector table address is fetched from 0028 and the interrupt number is added
WD16
k0, xmmword ptr [rcx+rax*8]{uint8} - vector load with data conversion APX: VMOVDQA32 zmm0, [rcx+r16*8] - vector load with one of the new APX extended-GPRs
List of discontinued x86 instructions
List_of_discontinued_x86_instructions
API of the MS-DOS operating system
is the list of functions provided via the DOS API primary software interrupt vector. MS-DOS – most widespread implementation PC DOS – IBM OEM version of
DOS_API
Fault initiated by x86 processors due to an access violation
manual from 1986. A general protection fault is implemented as an interrupt (vector number 13 (0Dh)). Some operating systems may also classify some exceptions
General_protection_fault
ZX Spectrum technical feature
in instruction fetch cycles if the programmer has configured the interrupt vector table to fall within the contended area. In that case the ULA will decline
Contended_memory
Open-source CPU instruction set architecture
ARM's Scalable Vector Extension. That is, each vector in up to 32 vectors is the same length. The application specifies the total vector width it requires
RISC-V
64-bit extension of the ARM architecture
128-bit translation tables (ARMv9 only). Scalable Matrix Extension 2 (SME2) (ARMv9 only). Multi-vector instructions. Multi-vector predicates. 2b/4b weight
AArch64
CMOS microprocessor in the 6502 family
addressing modes, including zero page addressing. Vector pull (VPB) output indicates when interrupt vectors are being addressed. Memory lock (MLB) output
WDC_65C02
8-bit microcontroller family
total of seven. There is an overflow flag, and a second interrupt enable bit, allowing four interrupt priority levels. STM8AF automobile STM8AL automobile
STM8
IBM's 64-bit instruction set architecture implemented by its mainframe computers
last instruction that broke the sequential execution of instructions; an interrupt stores the BEAR in the doubleword at real address 272 (11016). After an
Z/Architecture
Computer science process
the low nibble of the interrupt vector, thus creating anything from INT 80h to 8Fh. […] The interrupt handler for all those vectors is the same. It will
Dynamic_dispatch
8-bit microprocessor
fixed vector interrupt system, mode 1, for simple systems with minimal hardware (with mode 0 being the 8080-compatible mode). A non-maskable interrupt (NMI)
Zilog_Z80
Family of RISC-based computer architectures
software. Further, a new Fast Interrupt reQuest mode, FIQ for short, allowed registers 8 to 14 to be replaced as part of the interrupt itself. This meant FIQ
Arm_architecture_family
Group of 32-bit RISC processor cores
choices. Interrupts: 1 to 32 (M0/M0+/M1), 1 to 240 (M3/M4/M7/M23), 1 to 480 (M33/M35P/M52/M55/M85). Wake-up interrupt controller: Optional. Vector Table Offset
ARM_Cortex-M
Digital electronic circuit
Applications of priority encoders include their use in interrupt controllers (to allow some interrupt requests to have higher priority than others), decimal
Priority_encoder
Processor register which changes or controls the general behavior of a CPU
other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor
Control_register
Instruction set architecture developed by Digital Equipment Corporation
and places on the bus the memory address of the two-word vector that points to its interrupt service routine address and a new PSW. The processor saves
PDP-11_architecture
Method of transferring program control to another part of a program
known as transfer vector, this method is also more recently known under such different names as "dispatch table" or "virtual method table" but essentially
Branch_table
source arguments to replicate a single value to all lanes of a vector calculation. The tables below provide indications of whether opmasks and broadcasts
List_of_x86_SIMD_instructions
16-bit IBM minicomputer introduced in 1965
register XR3 must point to the transfer vector entries for the library routines rather than a dispatch table of only their addresses, because this latter
IBM_1130
Family of instruction set architectures
have included: FRED (Flexible Return and Event Delivery) a modernized interrupt model designed to reduce latency, ChkTag (x86 Memory Tagging) to combat
X86
Call by which a computer process terminates its execution
Function 1: exit() MOV EBX, 0 ; Return code INT 80h ; # Passes control to interrupt vector # invokes system call—in this case system call # number 1 with argument
Exit_(system_call)
16-bit microprocessor introduced by NEC
8080 emulation. The operand of the instruction specifies an interrupt number whose vector contains the segment:offset where emulation is to begin. To
NEC_V20
Line of computers sold by Digital Equipment Corporation
Endianness Little Page size 512 bytes Extensions PDP-11 compatibility mode, VAX Vector Extensions, VAX Virtualization Extensions Open No Predecessor PDP-11 Successor
VAX
8-bit microprocessor from 1975
disabled or re-vectored during BCD math operations. This issue was addressed in the CMOS derivatives also, by making reset and all interrupts automatically
MOS_Technology_6502
Firmware to add BIOS support for a device
post-2000 BIOSes. The standard presents the notion of a Boot Connection Vector (BCV) table and BCV priority. The core principles of the standard make behaviour
Option_ROM
Guidance and navigation computer used in Apollo spacecraft
and a parity alarm panel light was illuminated. The AGC had five vectored interrupts: Dsrupt was triggered at regular intervals to update the user display
Apollo_Guidance_Computer
8-bit microprocessor
Interrupt Enable flag, despite the INTE output going inactive. As a result, the CPU enters a microcode loop, continuously acknowledging the interrupt
KR580VM80A
64 bit RISC architecture by Donald Knuth
vector. rK, the interrupt mask register Used to enable and disable specific interrupts. rQ, the interrupt request register Used to record interrupts as
MMIX
Multi-core microcontroller
then vectors to the designated interrupt service routine. After handling the interrupt, the service routine executes a return from interrupt instruction
Parallax_Propeller
Quickly accessible working storage available as part of a digital processor
registers hold read-only values such as zero, one, or pi. Vector registers hold data for vector processing done by SIMD instructions (Single Instruction
Processor_register
64-bit extension of x86 architecture
generally superseded by a set of sixteen 128-bit vector registers (XMM registers). Each of these vector registers can store one or two double-precision
X86-64
16-bit microprocessor
software interrupt vectors each consist of a pair of PC and WP values, so the register context switch is automatically performed by an interrupt as well
TMS9900
Series of 16-bit minicomputers
itself, as it informs the processor of the address of its own interrupt vector. Interrupt vectors are blocks of two 16-bit words in low kernel address space
PDP-11
Microprocessor development board
including interrupt servicing. Users are able to develop their own interface routines, and substitute new vectors for the original vectors in the startup
SYM-1
Family of backward-compatible assembly languages
of an address, it uses an interrupt vector, an index into a table of interrupt handler addresses. Typically, the interrupt handler saves all other CPU
X86_assembly_language
Instruction for x86 microprocessors
AVX-512 vector registers), and supervisor-state (state items that affect the application but are not directly user-visible, e.g. user-mode interrupt configuration)
CPUID
1993 American film
the cover-up, and then Morton commits suicide. Connor, Smith, and Jingo interrupt the merger negotiations to show Nakamoto President Yoshida the surveillance
Rising_Sun_(1993_film)
Microprocessor instruction set
unlike IN A,n RETN and RETI are identical and restore IFF1. Z80 compatible interrupt devices watch for RETI by sniffing the data bus while M1- is asserted
Z80_instruction_set
System routines for Classic Mac OS
by an operating system. Further, they each had their own dedicated interrupt vector, separate from the generic illegal opcode handler. As 1111 was reserved
Macintosh_Toolbox
Network packet distribution with multiple cores
in the kernel, right after the NIC driver. Having handled the network interrupt and before it can be processed, the packet is sent to the receiving queue
Multi-core network packet steering
Multi-core_network_packet_steering
Hardware that translates virtual addresses to physical addresses
user and supervisor states. Interrupts and traps do not switch contexts, which requires that all valid interrupt vectors always be mapped in page 0 of
Memory_management_unit
Configuration in computer memory
addresses to the underlying fragmented physical addresses. Thus, the use of vectored I/O (scatter-gather lists) can sometimes be avoided. Devices that do not
Input–output memory management unit
Input–output_memory_management_unit
Type of defect in crystalline materials
a perfect line dislocation in FCC has the burgers vector ½<110>, which is a translational vector. Splitting into two partial dislocations is favorable
Stacking_fault
Process performed by firmware or software routines
of the BIOS code itself verify some basic components like DMA, timer, interrupt controller initialize, size, and verify system main memory initialize
Power-on_self-test
CPU microarchitecture by Intel
Technology, which introduced Extended Page Table support, virtual processor identifiers (VPIDs), and non-maskable interrupt-window exiting. SSE4.2 and POPCNT instructions
Nehalem_(microarchitecture)
Statistics applied to risk in insurance and other financial products
Historically, actuarial science used deterministic models in the construction of tables and premiums. The science has gone through revolutionary changes since the
Actuarial_science
8-bit microprocessor
extensions to support new interrupts, with three maskable vectored interrupts (RST 7.5, RST 6.5 and RST 5.5), one non-maskable interrupt (TRAP), and one externally
Intel_8085
vector and a vir helper plasmid. The two plasmids are used together (thus binary) to produce genetically modified plants. They are artificial vectors
Transfer_DNA_binary_system
Protocol for communicating routing information on the Internet
among autonomous systems (AS) on the Internet. BGP is classified as a path-vector routing protocol, and it makes routing decisions based on paths, network
Border_Gateway_Protocol
ARM Cortex-M based Microcontrollers by STMicroelectronics
common microcontrollers Embedded system, Single-board microcontroller Interrupt, Interrupt handler, Comparison of real-time operating systems "STM32 32-bit
STM32
1987 novel by Raymond E. Feist and Janny Wurts
17, Mara's ceremonial pledge of servantship to the goddess Lashima is interrupted by the news that her father and brother have been killed in battle. Now
Daughter_of_the_Empire
Family of computers 1970–1990
Extensions Storage-Key 4K-Byte Block Suspend and Resume Test Block Translation Vector 31-Bit IDAWs When the first System/370 machines, the Model 155 and the Model
IBM_System/370
Games from the 1940s to the 1970s
include a cathode ray tube (CRT), oscilloscope, liquid crystal display, or vector-scan monitor. This definition would preclude early computer games that outputted
Early_history_of_video_games
Low-level programming language family
drivers and interrupt handlers. In an embedded processor or DSP, high-repetition interrupts require the shortest number of cycles per interrupt, such as
Assembly_language
Boot sector of non-partitioned media in PC systems
Table (DPT/FDPB) is typically set up at 0000h:0078h in memory already, the VBR must move (and possibly fix-up) the DPT pointed to by INT 1Eh vector to
Volume_boot_record
Mosquito-borne disease
which primarily rely on interrupting the human mosquito contact during nighttime indoor feeding. Therefore, incorporating vector behavioral changes into
Malaria
8-bit microcontroller
instruction executed must be in the same 256-byte page of ROM as the table itself, a 256-entry table is not possible. Only on "feature family" (COP888/COP8SA) cores;
COP8
Series of microarchitectures and instruction set architecture by AMD
scheduler a Branch & Message Unit 4 16-lane-wide SIMD Vector Units (SIMD-VUs) 4 64 KiB vector general-purpose register (VGPR) files 1 scalar unit (SU)
Graphics_Core_Next
Type of interaction between species
parasitism (by contact), trophically-transmitted parasitism (by being eaten), vector-transmitted parasitism, parasitoidism, and micropredation. One major axis
Parasitism
Family of block-oriented display terminals and printers made by IBM
and minimizes the data transmitted. Some users familiar with character interrupt-driven terminal interfaces find this technique unusual. There is also
IBM_3270
semiconductor transport. Assuming the carrier motion consists of free flights interrupted by scattering mechanisms, a computer is utilized to simulate the trajectories
Monte Carlo methods for electron transport
Monte_Carlo_methods_for_electron_transport
Computer display mode based on characters
graphics but for which the expense of a framebuffer could not be justified, vector displays were a popular workaround. But there were many computer applications
Text_mode
16-bit microprocessor
set aside as a set of pointers, or vectors, to the code handling a particular device. The devices causing the interrupt then set some state, typically via
Zilog_Z8000
Microprocessor stack machine
has a single edge-sensitive interrupt, with a vector consisting of 32 bytes of code space beginning at address 32. Vectors 2 through 63 each have 32 bytes
ZPU_(processor)
identification vector. In all 2048 such vectors were available. The "ident" instruction determined which device was giving an interrupt. The identification
Nord-10
2025 American television series
Ingrid's earlier sabotage. He is able to scramble together enough of a vector to make a working cure, but reveals to the team that it will only be enough
Watson_(TV_series)
Free Unix-like operating system kernel
priorities. With kernel preemption, the kernel can preempt itself when an interrupt handler returns, when kernel tasks block, and whenever a subsystem explicitly
Linux_kernel
File format and programming language
printer to printer, requiring program authors to create numerous drivers. Vector graphics printing was left to special-purpose devices, called plotters.
PostScript
Type of adjustable-speed drive
special multi-point V/Hz paths. The two other drive control platforms, vector control and direct torque control (DTC), adjust the motor voltage magnitude
Variable-frequency_drive
INTERRUPT VECTOR-TABLE
INTERRUPT VECTOR-TABLE
Boy/Male
American, British, Christian, Danish, Dutch, English, Finnish, French, German, Greek, Hindu, Indian, Irish, Jamaican, Latin, Romanian, Slovenia, Spanish, Swedish, Swiss, Tamil, Ukrainian
Victorious; Conqueror; Winner; Champion; One who Conquers; Victory
Male
English
Roman Latin name VICTOR means "conqueror."Â
Male
English
Short form of English Sylvester, VESTER means "from the forest."
Boy/Male
Spanish American Shakespearean Greek Latin
Tenacious.
Surname or Lastname
Scottish
Scottish : Anglicized form of the Gaelic personal name Eachann (earlier Eachdonn, already confused with Norse Haakon), composed of the elements each ‘horse’ + donn ‘brown’.English : found in Yorkshire and Scotland, where it may derive directly from the medieval personal name. According to medieval legend, Britain derived its name from being founded by Brutus, a Trojan exile, and Hector was occasionally chosen as a personal name, as it was the name of the Trojan king’s eldest son. The classical Greek name, HektÅr, is probably an agent derivative of Greek ekhein ‘to hold back’, ‘hold in check’, hence ‘protector of the city’.German, French, and Dutch : from the personal name (see 2 above). In medieval Germany, this was a fairly popular personal name among the nobility, derived from classical literature. It is a comparatively rare surname in France.
Boy/Male
Christian & English(British/American/Australian)
Conqueror
Boy/Male
Latin American Spanish
Conqueror.
Male
Greek
(á¼ÎºÏ„ωÏ) Variant spelling of Greek Hektor, EKTOR means "defend; hold fast."
Male
Portuguese
Galician-Portuguese form of Roman Latin Victor, VITOR means "conqueror."
Male
Arthurian
, sir Hector de Maris; (defender).
Boy/Male
Australian, Basque, Czech, Czechoslovakian, Danish, Finnish, French, German, Hungarian, Latin, Polish, Slovenia, Swedish, Swiss, Ukrainian
The Conqueror; Victory; Victorious; Conquer
Boy/Male
English American
Doctor; teacher.
Boy/Male
American, Australian, British, Chinese, Christian, Danish, Dutch, English, French, German, Greek, Italian, Latin, Portuguese, Shakespearean, Spanish
Steadfast; Anchor; Holds Fast; Star; Coined from Esther Vanhomrigh; Tenacious; Defend; Hold Fast; Coined from Esther Vanho
Boy/Male
Native American
He interrupts.
Male
Russian
(Cyrillic Виктор): Slavic form of Roman Latin Victor, VIKTOR means "conqueror." In use by the Bulgarians, Russians and Serbians. Compare with another form of Viktor.
Male
Scandinavian
 Scandinavian form of Roman Latin Victor, VIKTOR means "conqueror." Compare with another form of Viktor.
Male
English
 Anglicized form of Scottish Gaelic Eachann, HECTOR means "brown horse." Compare with another form of Hector.
Boy/Male
Spanish
Victor.
Male
Portuguese
Portuguese form of Latin Hector, HEITOR means "defend; hold fast."
Boy/Male
Christian & English(British/American/Australian)
Steadfast
INTERRUPT VECTOR-TABLE
INTERRUPT VECTOR-TABLE
Surname or Lastname
English
English : variant spelling of Hollifield.
Girl/Female
Bengali, Gujarati, Hindu, Indian, Jain, Kannada, Malayalam, Marathi, Tamil, Telugu
Wisdom; Intelligence; Other Name of Goddess Saraswati
Boy/Male
Hindu, Indian, Punjabi, Sikh
Praise of the God
Surname or Lastname
Irish
Irish : reduced Anglicized form of Gaelic Ó Duinn, Ó Doinn ‘descendant of Donn’, a byname meaning ‘brown-haired’ or ‘chieftain’.English : nickname for a man with dark hair or a swarthy complexion, from Middle English dunn ‘dark-colored’.Scottish : habitational name from Dun in Angus, named with Gaelic dùn ‘fort’.Scottish : nickname from Gaelic donn ‘brown’. Compare 1.
Girl/Female
Arabic, Muslim
Derived from Sarah
Surname or Lastname
Americanized spelling of German Kast.English (Essex, Kent)
Americanized spelling of German Kast.English (Essex, Kent) : possibly a nickname from Norman caste ‘chaste’, ‘virtuous’ (from Old French chaste).Possibly an altered spelling of French Caste, cognate with 2.
Boy/Male
Muslim/Islamic
Prince the honest and kind. Peace and truth
Boy/Male
Hindu
Boy/Male
Tamil
God of land
Boy/Male
Hindu
Sarvaniki endrudu
INTERRUPT VECTOR-TABLE
INTERRUPT VECTOR-TABLE
INTERRUPT VECTOR-TABLE
INTERRUPT VECTOR-TABLE
INTERRUPT VECTOR-TABLE
v. t.
To obstruct or interrupt the progress of; to stop; to hinder or oppose; as, to intercept the current of a river.
n.
The ratio of one vector to another in length, no regard being had to the direction of the two vectors; -- so called because considered as a stretching factor in changing one vector into another. See Versor.
n.
One who, or that which, interrupts.
p. a.
Broken; interrupted.
n.
A term made up of the two parts / + /1 /-1, where / and /1 are vectors.
v. t.
To tamper with and arrange for one's own purposes; to falsify; to adulterate; as, to doctor election returns; to doctor whisky.
v. t.
To divide; to separate; to break the monotony of; as, the evenness of the road was not interrupted by a single hill.
imp. & p. p.
of Interrupt
p. pr. & vb. n.
of Interrupt
n.
The turning factor of a quaternion.
n.
A belly, or protuberant part; a broad surface; as, the venter of a muscle; the venter, or anterior surface, of the scapula.
v. t.
To interrupt communication with, or progress toward; to cut off, as the destination; to blockade.
a.
Pertaining to a rector or a rectory; rectoral.
n.
Same as Radius vector.
v. t.
To break into, or between; to stop, or hinder by breaking in upon the course or progress of; to interfere with the current or motion of; to cause a temporary cessation of; as, to interrupt the remarks speaking.
n.
A woman who wins a victory; a female victor.
n.
A directed quantity, as a straight line, a force, or a velocity. Vectors are said to be equal when their directions are the same their magnitudes equal. Cf. Scalar.
v. t.
To confer a doctorate upon; to make a doctor.
n.
An African weaver bird (Textor alector).
v. t.
To take or seize by the way, or before arrival at the destined place; to cause to stop on the passage; as, to intercept a letter; a telegram will intercept him at Paris.