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Research project into RISC-based microprocessor design
Berkeley RISC is one of two seminal research projects into reduced instruction set computer (RISC) based microprocessor design taking place under the
Berkeley_RISC
Processor executing one instruction in minimal clock cycles
Stanford MIPS and Berkeley RISC. These were commercialized in the 1980s as the MIPS and SPARC systems. IBM eventually produced RISC designs based on further
Reduced instruction set computer
Reduced_instruction_set_computer
Open-source CPU instruction set architecture
without paying royalties. RISC-V was developed in 2010 at the University of California, Berkeley as the fifth generation of RISC processors created at the
RISC-V
American computer pioneer and academic (born 1947)
computer (RISC) design, having coined the term RISC, and by leading the Berkeley RISC project. As of 2018, 99% of all new chips use a RISC architecture
David Patterson (computer scientist)
David_Patterson_(computer_scientist)
Family of RISC-based computer architectures
1983 decision to begin their own CPU design, the Acorn RISC Machine. The original Berkeley RISC designs were in some sense teaching systems, not designed
ARM_architecture_family
Public university in Berkeley, California
pure form in 1935. Berkeley RISC – David Patterson leads ARPA's VLSI project of microprocessor design 1980–1984. Berkeley UNIX/Berkeley Software Distribution
University of California, Berkeley
University_of_California,_Berkeley
Family of RISC microprocessors and microcontrollers
32-bit RISC microprocessors and microcontrollers developed and fabricated by Advanced Micro Devices (AMD). Based on the seminal Berkeley RISC, the 29k
AMD_Am29000
Topics referred to by the same term
RISC in Wiktionary, the free dictionary. RISC is an abbreviation for reduced instruction set computer. RISC or Risc may also refer to: Berkeley RISC Classic
RISC_(disambiguation)
RISC processor architecture
RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs
DLX
RISC instruction set architecture
(RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system
SPARC
British computer manufacturer
(LISA influence, Berkeley RISC, Fabrication date), April 1998, Electronics Weekly "The history of the ARM CPU", taken from 'The ARM RISC Chip: A Programmers'
Acorn_Computers
DARPA project for very large integration of semiconductors
history. Its offspring include Berkeley Software Distribution (BSD) Unix, the reduced instruction set computer (RISC) processor concept, many computer-aided
VLSI_Project
Building at the University of California, Berkeley, United States
and Randy Katz, the Berkeley RISC series of processors were developed, pioneering Reduced Instruction Set Computing. The Berkeley RISC architecture was commercialized
Evans_Hall_(UC_Berkeley)
Subroutines in computer science
not allocating a register window on CPU architectures descended from Berkeley RISC. The term "leaf" refers to their position as leaf nodes in the call
Leaf_routine
Research project into RISC-based microprocessor design
effective exploitation of RISC architectures with optimizing compilers. MIPS, together with the IBM 801 and Berkeley RISC, were the three research projects
Stanford_MIPS
CPU architecture feature to improve performance
function calls and returns. One of the most influential features of the Berkeley RISC design, they were later implemented in instruction set architectures
Register_window
Hewlett-Packard FOCUS; Intel 80186, 80188, 80286; DEC J-11; Berkeley RISC-I 1983 Stanford MIPS; Berkeley RISC-II 1984 Motorola 68020; National Semiconductor 32032;
History of computing hardware (1960s–present)
History_of_computing_hardware_(1960s–present)
American computer engineer
architecture, including the open RISC-V instruction set and Agile hardware". Asanović received a PhD in computer science from Berkeley in 1998 under John Wawrzynek
Krste_Asanović
RISC instruction set architecture
microcode itself was the problem. He soon started the Berkeley RISC project. The emergence of RISC sparked off a long-running debate within the computer
DEC_PRISM
Private university in California, US
researchers working on radar equipment. RISC – ARPA funded VLSI project of microprocessor design. Stanford and UC Berkeley are most associated with the popularization
Stanford_University
Historical VLSI IC layout editor
to meet their needs in designing the SOAR CPU chip, a follow-on to Berkeley RISC. Fearing that Ousterhout was going to propose another name that started
Magic_(software)
reduced instruction set computer (RISC) processor architecture created by key developers of the MIPS and Berkeley RISC designs. DLX is a simplified version
List of educational programming languages
List_of_educational_programming_languages
Component of a computer's CPU
Retrieved 25 May 2019. Asanovic, Krste (2017). The RISC V Instruction Set Manual (PDF) (2.2 ed.). Berkeley: RISC-V Foundation. Power ISA (3.0B ed.). Austin:
Control_unit
RISC-based microprocessor design
Intel's i960 (or 80960) is a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller. It became a best-selling
Intel_i960
Organisation convention on night work for women in 1934 David Patterson Berkeley RISC, DLX, RISC-V, reduced instruction set computer R. Fabian Pease Professor at
List_of_electrical_engineers
Task of creating a processor
designed in 13 months by a group of about 9 people. The 32-bit Berkeley RISC I and RISC II processors were mostly designed by a series of students as part
Processor_design
implementation. While it is fair to say that Berkeley IRAM did not achieve the recognition that Berkeley RISC received, the IRAM project was nevertheless
Berkeley_IRAM_project
American computer manufacturer (1957–1998)
features equal to the best of DECs low-end minicomputer lineup. Worse, the Berkeley RISC and Stanford MIPS designs were aiming to introduce 32-bit designs that
Digital_Equipment_Corporation
Engineering school of the University of California, Berkeley
California, Berkeley College of Engineering (branded as Berkeley Engineering) is the engineering school of the University of California, Berkeley (a land-grant
UC Berkeley College of Engineering
UC_Berkeley_College_of_Engineering
American computer company
was marketed as a RISC machine, it was actually microprogrammed. It used a "sliding window" register model based on the Berkeley RISC processor, but memory
Pyramid_Technology
family are 32-bit RISC microprocessors. The Am29000 was a Berkeley RISC, register window design similar to the Sun SPARC. Am29000 32-bit RISC microprocessor
List of AMD Am2900 and Am29000 families
List_of_AMD_Am2900_and_Am29000_families
US telephony and computer company
featuring a RISC architecture "reasonably similar" to the SPARC architecture, having also been derived from the foundational Berkeley RISC work. This architectural
Computer_Consoles,_Inc.
Discontinued Unix operating system
RISC iX is a discontinued Unix operating system designed to run on a series of workstations based on the Acorn Archimedes microcomputer. Heavily based
RISC_iX
Professor of Computer Scientist, emeritus, at UC Berkeley; distinguished engineer at Google; pioneer of RISC computer design and RAID storage systems; 2017
List of University of California, Berkeley faculty
List_of_University_of_California,_Berkeley_faculty
Semiconductor manufacturing process
Wenzhong Bao and Peng Zhou announced that they had successfully created a 1nm RISC-V chip using two-dimensional semiconductors. In June 2026, IBM unveiled the
1_nm_process
American computer scientist (born 1952)
he began the MIPS project to investigate RISC processors, following preliminary investigations at Berkeley by David A. Patterson. On 1984, he used his
John_L._Hennessy
American fabless semiconductor design company
is most widely known for developing the MIPS architecture and a series of RISC CPU chips based on it. MIPS provides processor architectures and cores for
MIPS_Technologies
Microprocessor architecture and chipset
reduced instruction set computer (RISC) systems, although the description has been debated; the original Berkeley RISC and Stanford MIPS research programs
NCR/32
Open-source hardware description language (HDL)
Jonathan (ed.). "Chisel: Accelerating Hardware Design" (PDF). RISC-V. California, U.S.: RISC-V International. Schoeberl, Martin (August 30, 2019). Digital
Chisel_(programming_language)
originated from IBM's POWER ISA RISC-V, a RISC ISA that originated in 2010 at the University of California, Berkeley SPARC Bug Labs, a US technology company
List of open-source hardware projects
List_of_open-source_hardware_projects
Standard file format for executables, object code, shared libraries, and core dumps
Executable Format) Haiku, an open source reimplementation of BeOS RISC OS Stratus VOS, in PA-RISC and x86 versions SkyOS Fuchsia OS Z/TPF HPE NonStop OS Deos
Executable and Linkable Format
Executable_and_Linkable_Format
Fabless semiconductor company providing RISC-V processors
implemented the RISC-V ISA. In 2015, researchers Krste Asanović, Yunsup Lee, and Andrew Waterman from the University of California, Berkeley founded SiFive
SiFive
invented until many years later, when reduced instruction set computing (RISC) began to get market share. In many CISCs, an instruction could access either
History of general-purpose CPUs
History_of_general-purpose_CPUs
Graduate school in Shenzhen, Guangdong, China
RIOS Lab mainly conducts research in RISC-V hardware and software technology. The University of California, Berkeley is in the process of withdrawing from
Tsinghua Shenzhen International Graduate School
Tsinghua_Shenzhen_International_Graduate_School
spurred the development[citation needed] of Reduced Instruction Set Computers (RISC) whose instruction set architectures (ISAs) leverage a smaller set of core
Iron law of processor performance
Iron_law_of_processor_performance
First model of the second generation of the Apple Macintosh computer line
Technology 1991 RISC Data Book. Integrated Device Technology. 1991. pp. 8.71 – 8.74. Retrieved February 15, 2026. "MacStation™ 3 RISC Workstation in a
Macintosh_II
Order of bytes in a computer word
ordering for processor architectures (x86, most ARM implementations, base RISC-V implementations) and their associated memory. File formats can use either
Endianness
NeXTSTEP QNX Redox RISC iX SOX SunOS SerenityOS Ultrix uNETix Research Unix Comparison of BSD operating systems History of the Berkeley Software Distribution
List_of_Unix_systems
Improved version of the vi text editor
Windows starting from Windows NT 3.1, OS/2, OS/390, MorphOS, OpenVMS, QNX, RISC OS, Linux, BSD, and Classic Mac OS. Vim is also shipped with Apple macOS
Vim_(text_editor)
Chinese venture capitalist (born 1968)
Nanotechnologies, and StarFive. He serves as a member of the board of directors of the RISC-V International Association. Li has worked with Rao Jin's venture, April
Eric_X._Li
Line of workstation and server computer systems
can also run the Linux operating system. Some PA-RISC-based models are able to run NeXTSTEP. Berkeley Software Distribution (BSD) Unix was ported to the
HP_9000
Layer of hardware-level instructions or data structures
at the University of California, Berkeley, that introduced the term RISC. The industry responded to the concept of RISC with both confusion and hostility
Microcode
Family of 16-bit and 32-bit minicomputers
development of a new RISC processor, which emerged as the PA-RISC platform. The HP 3000 CPU was reimplemented as an emulator running on PA-RISC and a recompiled
HP_3000
Indian-American businessman (born 1955)
the Java programming language. Sun pioneered open systems technology and RISC processors, and focused on distributed systems. They sold networked servers
Vinod_Khosla
Free and open-source object relational database management system
ARMv6 in Raspberry Pi), RISC-V, z/Architecture, S/390, PowerPC (incl. 64-bit Power ISA), SPARC (also 64-bit), MIPS and PA-RISC. It was also known to work
PostgreSQL
American computer company, 1982–2010
to the evolution of several key computing technologies, among them Unix, RISC processors, thin client computing, and virtualized computing. At its height
Sun_Microsystems
Series of supercomputers by IBM
and Enhancements for SP1 IBM Announcement 996-181: Hardware Withdrawal: RISC System/6000 SP POWERquery and Selected Models and Features -- Replacements
IBM_RS/6000_SP
Sharing of data between running processes in a computer system
(WCF) Novell's SPX POSIX mmap, message queues, semaphores, and shared memory RISC OS's messages Solaris Doors System V's message queues, semaphores, and shared
Inter-process_communication
Series of Unix operating systems from IBM
computers such as IBM's Power line. Originally released for the IBM RT PC RISC workstation in 1986, AIX has supported a wide range of hardware platforms
IBM_AIX
NeXTSTEP (1.0) OS/2 (1.2) RISC OS (First release was to be called Arthur 2, but was renamed to RISC OS 2, and was first sold as RISC OS 2.00 in April 1989)
Timeline_of_operating_systems
for most POSIX compliant (Unix-like) operating systems, such as Linux, Berkeley Software Distribution (BSD), and macOS (Darling and Darwine projects).
List_of_emulators
American computer scientist
Engineering and Computer Science Department (EECS) at Berkeley where he introduced the concept of RISC processors with David A. Patterson in the early 1980s
Carlo_H._Séquin
Free and open-source Unix-like operating system
is a free and open-source Unix-like operating system descended from the Berkeley Software Distribution (BSD). The first version was released in 1993 developed
FreeBSD
released their own Risc PC compatible design, the Iyonix PC, which was produced until 2008. RISC OS continued beyond the end of the Risc PC in a limited
History_of_personal_computers
Software projects developed at universities
of Minnesota software Berkeley Software Distribution RISC-V – open-source hardware architecture developed at UC Berkeley lowRISC – open-source silicon
List of software developed at universities
List_of_software_developed_at_universities
Series of discontinued Unix operating systems by DEC
was released, the VAX and MIPS versions were referred to as VAX/ULTRIX and RISC/ULTRIX respectively. Much engineering emphasis was placed on supportability
Ultrix
Computer Sciences DARPA, News and events Electricity, Light, Join Forces to Advance Computing Chen Sun RISC-‐V Microprocessor Chip with Photonic I/O v t e
Photonically Optimized Embedded Microprocessors
Photonically_Optimized_Embedded_Microprocessors
Computer architecture bit width
Instruction Sets Should Be Free: The Case For RISC-V (PDF). EECS Department, University of California, Berkeley. UCB/EECS-2014-146. "Synopsys Introduces New
64-bit_computing
Computer architecture bit width
Asanović, Krste. "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.2". University of California, Berkeley. EECS-2016-118. Retrieved
128-bit_computing
Component of computer engineering
retroactively denoted "CISC" are in fact significantly simpler than modern RISC processors (in several respects). However, the choice of instruction set
Microarchitecture
Series of Unix workstations and servers
Sun-3 series, but employing microprocessors based on Sun's own SPARC V7 RISC architecture in place of the 68k family processors of previous Sun models
Sun-4
Lisp programming language system
California, Berkeley (UC Berkeley, UCB) by Professor Richard Fateman and several students, based largely on Maclisp and distributed with the Berkeley Software
Franz_Lisp
Free and open-source Unix-like operating system
and vintage home computers to modern ARM-based systems, Raspberry Pis, and RISC-V hardware. Portability is assisted by a hardware abstraction layer that
NetBSD
Enzyme that cleaves double-stranded RNA (dsRNA) into short dsRNA fragments
activation of the RNA-induced silencing complex (RISC), which is essential for RNA interference. RISC has a catalytic component Argonaute, which is an
Dicer
with a macOS interface. CheriBSD – adapted to support CHERI-MIPS, CHERI-RISC-V, and Arm Morello ISAs. NetBSD aims to provide a freely redistributable
Comparison of BSD operating systems
Comparison_of_BSD_operating_systems
Operating system
of system architectures including x86-64, IA-32, ARM, PowerPC, and 64-bit RISC-V. Its default GUI is FVWM on X11. In December 1994, Theo de Raadt, a founding
OpenBSD
1993 personal digital assistant
devices was undertaken in Japan by Sharp. The devices are based on the ARM 610 RISC processor, run Newton OS, and all feature handwriting recognition software
MessagePad
Punctuation to signal the end of a sentence (.)
extension of a file name from the name of the file (e.g., filename.mp4). RISC OS uses dots to separate levels of the hierarchical file system when writing
Full_stop
Topics referred to by the same term
OberonStation package The RISC-V instruction set architecture derived from designs that originated at University of California, Berkeley, and supported by multiple
RISC5
Line of computers sold by Digital Equipment Corporation
typical workload. As Unix RISC systems from Sun Microsystems and others lured VAX customers, In 1989 DEC introduced a range of RISC workstations and servers
VAX
Linux distribution
others. It is officially supported and considered stable on IA-32, x86-64, PA-RISC, 32-bit and 64-bit PowerPC, 64-bit SPARC, DEC Alpha, and 32- and 64-bit ARM
Gentoo_Linux
American software developer
Millbrae, California. Although seeking to enter the market for Unix products on RISC-based systems, such as a version of System V Release 4 for MIPS, the company
UniSoft
American computer manufacturer
produced the first commercially available Reduced instruction set computer (RISC) systems. Ridge Computers was established in May 1980 in Santa Clara, California
Ridge_Computers
Project in integrated circuit design
foundation of the OpenLane and ChipIgnite projects, the open-source ecosystem for RISC-V System-on-Chip (SoC) designs has expanded rapidly and is now considered
OpenROAD_Project
Source-level debugger
x86 (32-bit and 64-bit), IA-64 "Itanium", Motorola 68k, MIPS, PA-RISC, PowerPC, RISC-V, SuperH, SPARC, and VAX. Lesser-known target processors supported
GNU_Debugger
Research distributed operating system
work on his personal homepage, which include the 64-bit 9k kernel and a RISC-V port. Unofficial development for the system also continues on the 9front
Plan_9_from_Bell_Labs
Operative System
operating systems courses. It was developed at the University of California, Berkeley, designed by Thomas Anderson, and is used by numerous schools around the
Not Another Completely Heuristic Operating System
Not_Another_Completely_Heuristic_Operating_System
Microcontroller software based on Python
MicroPython version 1.9.4. In 2017, Microsemi made a MicroPython port for RISC-V (RV32 and RV64) architecture. In April 2019, a version of MicroPython for
MicroPython
Object-oriented programming language similar to Eiffel
(implementation of Sather version 1.3); Peter Naulls' port of ICSI Sather 1.1 to RISC OS; and pSather, a parallel version of ICSI Sather addressing non-uniform
Sather
American computer scientist
hardware for his own research explorations. Because the impetus for the RISC-V development was the paucity of open-source processor designs for the RAMP
Charles_P._Thacker
Spanish actress
October 2024. "Premis Gaudí: "El 47" triomfa en una gala que també reconeix el risc de "Polvo serán"". 3/24. 19 January 2025 – via 3Cat. Wikimedia Commons has
Ángela_Molina
Computer specialized in running Lisp
Müller-Schloer (1988), "Bewertung der RISC-Methodik am Beispiel COLIBRI", in Bode, A (ed.), RISC-Architekturen [Risc architectures] (in German), BI Hafer
Lisp_machine
that RISC technology had much better performance per cost than traditional computer architectures. Minicomputer vendors developed their own RISC-based
History_of_Unix
GNU implementation of the standard C library
DEC Alpha, IA-64, Motorola m68k, MicroBlaze, MIPS, Nios II, PA-RISC, PowerPC, RISC-V, s390, SPARC, and x86 (old versions support TILE). It officially
Glibc
Database project devoted to the ranking of computers
including the top eight supercomputers. 15 other supercomputers are all based on RISC architectures, including six based on ARM64 and seven based on the Power
TOP500
American annual computer science prize
large systems and the development of reduced instruction set computers (RISC); for discovering and systematizing many fundamental transformations now
Turing_Award
Multi-core microprocessor microarchitecture
Broadband Engine (Cell/B.E.) is a 64-bit reduced instruction set computer (RISC) multi-core processor and microarchitecture developed by Sony, Toshiba, and
Cell_(processor)
Processor with an instruction set customized (optimized) for a specific task
UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES Waterman, Andrew Lee, Yunsup Patterson, David A Asanovi (May 6, 2014). The RISC-V Instruction
Application-specific instruction set processor
Application-specific_instruction_set_processor
Computer designed to run a specific language
of optimizing compilers and reduced instruction set computer (RISC) architectures and RISC-like complex instruction set computer (CISC) architectures, and
High-level language computer architecture
High-level_language_computer_architecture
UNIX workstation series
functionality in both the CISC and RISC versions. The NEWS-OS 4.x series was also released in both CISC and RISC versions. Yukihiro Matsumoto originally
Sony_NEWS
BERKELEY RISC
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