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Instructions for the x86 microprocessors
Wikibooks has a book on the topic of: X86 Assembly/AVX, AVX2, FMA3, FMA4 Advanced Vector Extensions (AVX, also known as Gesher New Instructions and then
Advanced_Vector_Extensions
Instruction set extension by Intel
AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel
AVX-512
Topics referred to by the same term
set AVX-512, 512-bit extensions to the 256-bit AVX Softwin AVX (AntiVirus eXpert), former name of Bitdefender Aviapaslauga (ICAO airline code AVX); see
AVX
2012 Marvel comic book series
Avengers vs. X-Men (AvX or AvsX) is a 2012 crossover storyline that was featured in comic books published by Marvel Comics. The event, consisting of an
Avengers_vs._X-Men
American electronic component manufacturer
AVX Corporation is an American manufacturer of electronic components headquartered in Fountain Inn, South Carolina. It is the largest industrial employer
AVX_Corporation
AMD 3-nanometre processor microarchitecture
introduce new instruction extensions, including AVX512_BMM, AVX_NE_CONVERT, AVX_IFMA, AVX_VNNI_INT8, and AVX512_FP16. It is also expected that Zen 6 will
Zen_6
32-bit mode) AVX: 128-bit vectors, operating on xmm0..xmm15 registers, with a new three-operand encoding enabled by the new VEX prefix. (AVX introduced
List_of_x86_SIMD_instructions
Family of instruction set architectures
SIMD registers XMM0–XMM15 (XMM0–XMM31 when AVX-512 is supported). SIMD registers YMM0–YMM15 (YMM0–YMM31 when AVX-512 is supported). Lower half of each of
X86
Type of parallel processing
architectures. Advanced vector extensions AVX, AVX2 and AVX-512 are developed by Intel. AMD supports AVX, AVX2, and AVX-512 in their current products. With
Single instruction, multiple data
Single_instruction,_multiple_data
American brand name of golf equipment
Titleist (pronounced /ˈtaɪtəlɪst/ "title-ist") is an American brand of golf equipment produced by the Acushnet Company, headquartered in Fairhaven, Massachusetts
Titleist
SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM Sempron and Athlon models exclude
List of AMD processors with 3D graphics
List_of_AMD_processors_with_3D_graphics
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX2, AVX-512, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an
List of Intel Xeon processors (Skylake-based)
List_of_Intel_Xeon_processors_(Skylake-based)
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, F16C, BMI1 (Bit Manipulation Instructions1), BMI2, Enhanced Intel SpeedStep
List of Intel Xeon processors (Haswell-based)
List_of_Intel_Xeon_processors_(Haswell-based)
US Army helicopter program
contracts for FARA candidates were awarded in April 2019 to five manufacturers: AVX Aircraft (in partnership with L3Harris Technologies), Bell Helicopter, Boeing
Future Attack Reconnaissance Aircraft
Future_Attack_Reconnaissance_Aircraft
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation)
List of Intel Xeon processors (Broadwell-based)
List_of_Intel_Xeon_processors_(Broadwell-based)
Planned family of US military helicopters
reduction in specific fuel consumption and weighs less than the T55 engine. AVX AVX Aircraft proposed an aircraft with their coaxial rotor and twin ducted
Future_Vertical_Lift
2024 AMD 4-nanometer processor microarchitecture
floating-point pipes compared to three pipes in Zen 4. Zen 4 introduced AVX-512 instructions. AVX-512 capabilities have been expanded with Zen 5 with a doubling
Zen_5
socket All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX-512, FMA3, MPX, Enhanced Intel SpeedStep Technology (EIST), Intel 64
List of Intel Xeon processors (Cascade Lake–based)
List_of_Intel_Xeon_processors_(Cascade_Lake–based)
Airport at Santa Catalina Island, California, United States
Catalina Airport (IATA: AVX, ICAO: KAVX, FAA LID: AVX) is a privately owned airport located 6.4 miles (10.3 km) northwest of the central business district
Catalina_Airport
Extensions (SSE), SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Advanced Vector Extensions (AVX), Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit
List of Intel Xeon processors (Ivy Bridge–based)
List_of_Intel_Xeon_processors_(Ivy_Bridge–based)
CPU microarchitecture by Intel
(HLAT) SERIALIZE Enhanced Hardware Feedback Interface (EHFI) and HRESET AVX-VNNI AVX-512 with AVX512-FP16 In server Sapphire Rapids CPUs: CLDEMOTE TSX with
Golden_Cove
CPU microarchitecture by Intel
256 entries (from 208) Improved branch prediction Support for AVX, AVX2, FMA3 and AVX-VNNI instructions 2 or 4 MB shared L2 cache per 4-core cluster
Gracemont_(microarchitecture)
Intel microprocessor family
immediate constants in the register renamer AVX-VNNI, a VEX-coded variant of AVX512-VNNI for 256-bit vectors AVX-512 (including FP16) is present but disabled
Alder_Lake
Series of x86 manycore processors from Intel
Instructions (AVX-512CD), Intel AVX-512 Exponential and Reciprocal Instructions (AVX-512ER), and Intel AVX-512 Prefetch Instructions (AVX-512PF). Support
Xeon_Phi
Software library for LLM inference
llama.cpp makes use of several CPU extensions for optimization: AVX, AVX2, AVX-512, AVX-VNNI and AMX for X86-64. Neon, i8MM, SVE, SVE2, SME and SME2 for
Llama.cpp
Extension to the x86 instruction set
operand are also defined: A EVEX vectorized version (VPCLMULQDQ) is seen in AVX-512. Intel Westmere processor (March 2010). Sandy Bridge processor Ivy Bridge
CLMUL_instruction_set
2024 Intel product line
of 32 bytes per cycle. Lion Cove P-cores include support for AVX-512 instructions but AVX-512 has been disabled in Arrow Lake processors due to its heterogenous
Arrow_Lake_(microprocessor)
Intel processor family
fabrication. Cannon Lake CPUs are the first mainstream CPUs to support the AVX-512 instruction set. Prior to Cannon Lake's launch, Intel launched another
Cannon_Lake_(microprocessor)
Computer security vulnerability
vulnerability which relies on speculative execution of Advanced Vector Extensions (AVX) instructions to reveal the content of vector registers. Intel's Software
Downfall (security vulnerability)
Downfall_(security_vulnerability)
Computer chip instruction set extension
Intel released processors in early 2011 with AVX support. AVX2 is an expansion of the AVX instruction set. AVX-512 (3.1 and 3.2) are 512-bit extensions to
Streaming_SIMD_Extensions
Canadian entertainment company
Beyond, featuring 20 minutes of the film optimised for this format. UltraAVX is Cineplex's in-house premium large format, referring to auditoriums with
Cineplex_Entertainment
Line of CPUs produced by Intel
mainstream CPUs to include the AVX-512 instruction set. In comparison to the previous generation AVX2 (AVX-256), the new generation AVX-512 most notably provides
Intel_Core
Japanese line of cameras
v t e Kyocera Subsidiaries and brands Current AVX Corporation Kyocera Communications Kyocera Unimerco Triumph-Adler Former Contax KLH Taito Yashica Products
Contax_T
AVX at all. No AMX. No XDNA. UHD Blu-ray playback not supported. Lacks hardware video codec. No longer supported. Not supported by Windows 11. No AVX
List of IOMMU-supporting hardware
List_of_IOMMU-supporting_hardware
Microarchitecture by AMD
available at its introduction (including SSSE3, SSE4.1, SSE4.2, AES, CLMUL, and AVX) as well as new instruction sets proposed by AMD; ABM, XOP, FMA4 and F16C
Bulldozer_(microarchitecture)
CPU microarchitecture by Intel
processors All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX-512, FMA3, MPX, Enhanced Intel SpeedStep Technology (EIST), Intel 64
Skylake_(microarchitecture)
Formerly called Gesher but renamed in 2007. First x86 to introduce 256 bit AVX instruction set and implementation of YMM registers. Ivy Bridge: successor
List of Intel CPU microarchitectures
List_of_Intel_CPU_microarchitectures
32 KB instruction) per core. L2 cache: 1 MB per core. All models support AVX-512 using a half-width 256-bit FPU. PCIe 4.0 support. Native USB 40Gbps (USB4)
List_of_AMD_Ryzen_processors
instructions differently for better compatibility with Intel's proposed AVX instruction set. The three SSE5-derived instruction sets were introduced
SSE5
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation)
List of Intel Xeon processors (Sandy Bridge–based)
List_of_Intel_Xeon_processors_(Sandy_Bridge–based)
Extension to the x86 instruction set
Wikibooks has a book on the topic of: X86 Assembly/AVX, AVX2, FMA3, FMA4 The FMA instruction set is an extension to the 128- and 256-bit Streaming SIMD
FMA_instruction_set
Instruction set extensions accelerating AES operations
Intel in March 2008. A wider version of AES-NI, AVX-512 Vector AES instructions (VAES), is found in AVX-512. The following Intel processors support the
AES_instruction_set
Set of cryptographic hash functions
code generated by gcc-5.x. On 64-bit x86, there are generic, AVX2, AVX-512, and AVX-512VL implementations. The plain version is about 15% faster than code
SHA-3
Upcoming microprocessor family by Intel
Instructions x86-64, IA-32 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX10.2, APX, AES-NI, SHA-NI, RDRAND, SM3, SM4, VT-x, VT-d Products
Nova_Lake_(microprocessor)
Intel processor family
otherwise. All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit
Intel Sandy Bridge-based Xeon microprocessors
Intel_Sandy_Bridge-based_Xeon_microprocessors
SSSE3, SSE4.1, SSE4.2, SSE4a, IOMMU, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, CVT16–F16C, XOP, FMA4. All models support single socket configurations Memory
List of AMD Opteron processors
List_of_AMD_Opteron_processors
Floating-point number format used in computer processors
utilized in many CPUs, GPUs, and AI processors, such as Intel Xeon processors (AVX-512 BF16 extensions), Intel Data Center GPU, Intel Nervana NNP-L1000, Intel
Bfloat16 floating-point format
Bfloat16_floating-point_format
SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM AMD in its technical documentation
List_of_AMD_Athlon_processors
Marketing name by Intel
two sets of features: AVX-512 VNNI, 4VNNIW, or AVX-VNNI: fast multiply-accumulation mainly for convolutional neural networks. AVX-512 BF16: lower-precision
DL_Boost
6th generation Xeon x86 server processors designed by Intel, released in 2024
the Redwood Cove cores in Granite Rapids are able to issue AVX-512 and newly added AVX-512-FP16 instructions. A compute tile also contains DDR5 memory
Granite_Rapids
Instruction set architecture extension for microprocessors
for microprocessors from Intel, AMD and others. It was introduced with the AVX instruction set. The VEX prefix consists of three bytes and can be added
VEX_prefix
2022 AMD 5-nanometer processor microarchitecture
bridge chip or chipset. Zen 4 is the first AMD microarchitecture to support AVX-512 instruction set extensions. 512-bit vector instructions are split in
Zen_4
Type of capacitor
Reynolds, AVX, Technical Information, Reliability Management of Tantalum Capacitors, PDF Archived 2013-08-06 at the Wayback Machine "J. Gill, AVX, Surge
Electrolytic_capacitor
64-bit extension of x86 architecture
unmodified on AMD64. For the VMASKMOVPS/VMASKMOVPD/VPMASKMOVD/VPMASKMOVQ (AVX/AVX2 masked move to/from memory) instructions, Intel 64 architecturally guarantees
X86-64
Transistors: TBD Package size: 37.5 mm x 37.5mm All models support: SSE4.1, SSE4.2, AVX, AVX2, FMA3, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit
List of Intel Pentium processors
List_of_Intel_Pentium_processors
CPU microarchitecture by Intel
512 KB per core) Larger L3 caches (3 MB per core from 2 MB per core) A new AVX-512 instruction: Vector Pair Intersection to a Pair of Mask Registers, VP2INTERSECT
Willow_Cove
Solid conductive electrolyte
Limitations" (PDF). AVX. Zednicek, T. "A Study of Field Crystallization in Tantalum Capacitors and its effect on DCL and Reliability" (PDF). AVX. "Panasonic Announces
Polymer_capacitor
Type of electrolytic capacitor
Zednicek, AVX, A Study of Field Crystallization in Tantalum Capacitors and its effect on DCL and Reliability, [4] P. Vasina, T. Zednicek, AVX, J. Sikula
Tantalum_capacitor
Intel microprocessor series released in 2023
instructions support for AI workloads but Crestmont E-cores still lack support for AVX-512 instructions due to lack of AVX10 support. Testing of Meteor Lake's new
Meteor_Lake
and eMMC 5.0 Serial I/O supporting SPI, HSUART (serial port) and I2C Lacks AVX, AVX2 and older SSE4.2 instruction sets. All models support: MMX, SSE, SSE2
List of Intel Celeron processors
List_of_Intel_Celeron_processors
Electrolytic Chip Capacitors High CV Consumer Series" (PDF). Datasheet. AVX Corporation. Archived (PDF) from the original on 28 December 2015. Retrieved
List of electronic component packaging types
List_of_electronic_component_packaging_types
Computer instruction set introduced by AMD in 2009
SSE5. It was changed to be similar but not overlapping with AVX, parts that overlapped with AVX were removed or moved to separate standards such as FMA4
XOP_instruction_set
memory. Underlined models support Intel vPro. Pentium and Celeron CPUs lack AVX and AVX2 support. Price is Recommended Customer Price (RCP) at launch. RCP
List_of_Intel_processors
American rapper
Rapper Singer Songwriter Producer Instrument Vocals Years active 2015–present Labels AVX The Foreign Affair Artist Originals Website anikkhanmusic.com
Anik_Khan
Airport. SLI POC CMA CNO EMT FUL WJF HHR PMD RAL SMO VCV VNY WHP TOA CCB AVX CPM AJO RIR Brackett Field (IATA: POC, ICAO: KPOC) is in La Verne. Camarillo
List of airports in the Los Angeles area
List_of_airports_in_the_Los_Angeles_area
Intel microprocessor released in 2021
(instructions-per-clock) DL Boost (low-precision arithmetic for Deep Learning) and AVX-512 instructions Compared to its predecessors, SGX instruction set extensions
Rocket_Lake
Intel microprocessor series released in 2026
Instructions set x86-64 Instructions x86, IA-32, x86-64 Extensions SSE4, AVX, AVX2, AVX-VNNI, AVX-IFMA AES-NI, SHA-NI, RDRAND, SM3, SM4 VT-x, VT-d P-core architecture
Panther_Lake_(microprocessor)
Canadian technology company
August 17, 2012. Team, Enough (March 13, 2014). "Motorola Solutions and AVX Expand Solutions for Hope in Democratic Republic of the Congo". The Enough
BlackBerry_Limited
Corporation AVA US Avnet Inc AVT US Avon Products, Inc. AVP United Kingdom Avx Corporation AVX US Axalta Coating Systems Ltd. AXTA US Axis Capital Holdings Limited
Companies listed on the New York Stock Exchange (A)
Companies_listed_on_the_New_York_Stock_Exchange_(A)
Marvel Comics superhero
imprisoned. Gillen portrays Cyclops as suicidal in a five-part epilogue: AvX: Consequences. Beast time-travels to meet the five original X-Men, explains
Cyclops_(Marvel_Comics)
Free and open-source web browser
along with any modern Linux distribution as long as the processors support AVX (64-bit) or SSE2 (32-bit) and there is at least 1 GB of RAM. OS X Lion and
Pale_Moon
Measure of computer performance
Goldmont) SSE3 (128-bit) 2 4 ? Intel Sandy Bridge (Sandy Bridge, Ivy Bridge) AVX (256-bit) 8 16 0 Intel Haswell (Haswell, Devil's Canyon, Broadwell) Intel
Floating point operations per second
Floating_point_operations_per_second
Intel microprocessor, released in 2024
x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 AVX, AVX2, FMA3, AVX-VNNI, AVX-IFMA, TSX VT-x, VT-d AES-NI, SHA, RDRAND E-core architecture
Sierra_Forest
GEOX Argo Group, AVX, BGR, Instaforex, Molex, Mouser, Neom, Robb Report, Rolling Stone, TTI, Variety, VIZIO 2019–20 Black, White Red AVX, Molex, Mouser
Formula E sponsorship liveries
Formula_E_sponsorship_liveries
City in South Carolina, United States
South Companies, Inc. (a subsidiary of Canfor) Vulcan Materials Company AVX Corporation Grainger Generating Station was a coal fired power plant operated
Conway,_South_Carolina
Type of memory addressing
development using AVX, AVX2, and AVX-512. Apress Media. ISBN 978-1-4842-7917-5. Hossain, Md Maruf; Saule, Erik (9 August 2021). "Impact of AVX-512 Instructions
Gather/scatter (vector addressing)
Gather/scatter_(vector_addressing)
Extensions to the x86 instruction set architecture
instruction set comprises AVX-based versions of the original SHA instruction set marked with a V prefix and these three new AVX-based instructions for SHA-512:
SHA_instruction_set
Intel microprocessors
cache. All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX
Intel Ivy Bridge–based Xeon microprocessors
Intel_Ivy_Bridge–based_Xeon_microprocessors
Emulator for PlayStation 3 software
recommended. Additional support for SIMD CPU instruction sets such as AVX-2 and AVX-512 is also recommended for best performance. Apart from the game itself
RPCS3
Type of computer instructions
noteworthy is a conflict detection instruction, VPCONFLICTD Also present in the AVX/AVX-512 GFNI subset is bit-matrix affine transformation and its inverse: GF2P8AFFINEQB
Bit_manipulation_instructions
AMD brand for microprocessors
Instructions sets: x87, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, CLMUL, AVX, AVX2, FMA3, CVT16/F16C, ABM, BMI1, BMI2, SHA. All Ryzen-branded CPUs (except
Ryzen
Experimental aircraft by Piasecki Aircraft
Archived 2013-05-02 at the Wayback Machine - Aviationweek.com, April 12, 2013 AVX joins Bell, Sikorsky/Boeing for Army's JMR-TD development - Flightglobal
Piasecki_X-49_SpeedHawk
Brand of computer chip
included an increased maximum number of cores, the Skylake microarchitecture, AVX-512 acceleration, and cryptographic acceleration. The second generation also
Xeon_D
German office equipment manufacturer
v t e Kyocera Subsidiaries and brands Current AVX Corporation Kyocera Communications Kyocera Unimerco Triumph-Adler Former Contax KLH Taito Yashica Products
Triumph-Adler
Small form factor PC designed by Intel
to: **SSE3** **SSSE3** **SSE4.1** Because AVX is completely absent, software compiled specifically for AVX instruction sets will not run on these processors
Next_Unit_of_Computing
Japanese ceramics and electronics company
global operations expanded significantly with the $650 million purchase of AVX Corporation, a global manufacturer of passive electronic components, such
Kyocera
Series of budget AMD microprocessors for personal computers
TeraScale 3 (VLIW4) MMX, SSE(1, 2, 3, S3, 4a, 4.1, 4.2), AMD64, AMD-V, AES, AVX, XOP, FMA(4, 3), CVT16, F16C, BMI(ABM, TBM), Turbo Core 3.0, NX bit PowerNow
Athlon_X4
Intel microprocessor family
branches) Indirect branch tracking and CET shadow stack Intel Key Locker AVX-512 extension support for most models Intel Xe-LP ("Gen12") GPU with up to
Tiger_Lake
Intel processor microarchitecture
window from 168 to 192 Queue Allocation from 28/threads to 56 Full 256-bit AVX Execution Units (from 128-bit) Wider core: fourth arithmetic logic unit (ALU)
Haswell_(microarchitecture)
2009 Microsoft operating system version
Vista. Windows 7 Service Pack 1 adds support for Advanced Vector Extensions (AVX), a 256-bit instruction set extension for processors, and improves IKEv2
Windows_7
Instruction encoding rule for the x86 instruction set
least-significant bits of a register index. Which register (general purpose, AVX, etc.) depends on the instruction being executed. Instructions which take
ModR/M
SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA3, FMA4, CVT16, F16C, Turbo Core Memory support: 1.35 V DDR3L-1600
List_of_AMD_mobile_processors
Gene therapy medication
2020. Archived from the original on 22 May 2020. Retrieved 21 April 2020. "AVXS-101 (Zolgensma) to be made available globally through a controversial programme"
Onasemnogene_abeparvovec
support for AVX-512 instruction set. AMD Zen 5 Family 1Ah – fifth generation Zen architecture, in 4 nm process. Adds support for full-width AVX-512 pipeline
List of AMD CPU microarchitectures
List_of_AMD_CPU_microarchitectures
identical to instructions in AVX-512 − later Xeon Phi processors replaced these instructions with AVX-512. Early versions of AVX-512 avoided the instruction
List of discontinued x86 instructions
List_of_discontinued_x86_instructions
16-bit computer number format
adopted by AMD and Intel CPUs by 2012. This was further extended up the AVX-512_FP16 instruction set extension implemented in the Intel Sapphire Rapids
Half-precision floating-point format
Half-precision_floating-point_format
Smartphone model
v t e Kyocera Subsidiaries and brands Current AVX Corporation Kyocera Communications Kyocera Unimerco Triumph-Adler Former Contax KLH Taito Yashica Products
Kyocera_Echo
Computer instruction for returning hardware-generated random numbers
SSSE3 (2006) SSE4 (2006) SSE5 (2007) AVX (2008) F16C (2009) XOP (2009) FMA (FMA4: 2011, FMA3: 2012) AVX2 (2013) AVX-512 (2015) AMX (2022) AVX10 (2023) Bit
RDRAND
Series of high-end microprocessors by AMD
Instruction set AMD64/x86-64, MMX(+), SSE1, 2, 3, 3s, 4.1, 4.2, 4a, AES, CLMUL, AVX, XOP, FMA3, FMA4, CVT16/F16C, BMI1, ABM, TBM, AMD-V Products, models, variants
AMD_FX
Romanian cybersecurity technology company
It was originally sold as AVX (Antivirus Expert) from 1996 until 2001, when the Bitdefender subsidiary was created and AVX was rebranded under the Bitdefender
Bitdefender
AVX
AVX
AVX
AVX
Boy/Male
Bengali, Gujarati, Hindu, Indian, Kannada, Malayalam, Marathi, Mythological, Oriya, Telugu
Lord Shiva
Boy/Male
Sikh
One imbued by the blissful soul
Biblical
son of my people
Girl/Female
Indian
Prosperous, Self-possessed, River, Ocean, River
Male
English
Pet form of English Murdoch, MURDY means "sea warrior."
Boy/Male
Hindu
A worshipper of Lord Shiva
Girl/Female
Tamil
Chanakshi | சாநாகà¯à®·à¯€Â
Boy/Male
German, Greek, Hungarian
Legend; Lover of Horses
Girl/Female
Gujarati, Hindu, Indian
Lord Sai Baba
Girl/Female
American, Australian, British, English, German
Hazelnut; Variant of Medieval Given Names Avis and Aveline
AVX
AVX
AVX
AVX
AVX