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Computer instruction for returning hardware-generated random numbers
RDRAND (for "read random") is an instruction for returning random numbers from an Intel on-chip hardware random number generator which has been seeded
RDRAND
AMD-V, AES, CLMUL, AVX, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core Single- or dual-channel DDR3 or DDR4 memory controller Third
List of AMD processors with 3D graphics
List_of_AMD_processors_with_3D_graphics
Creating sequence of numbers that cannot be predicted
in Linux, it is seen as unacceptable to use Intel's RDRAND hardware RNG without mixing in the RDRAND output with other sources of entropy to counteract
Random_number_generation
AMD-V, AES, CLMUL, AVX, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core Dual-channel DDR3 or DDR4 memory controller Boxed part with
List_of_AMD_Athlon_processors
Upcoming microprocessor family by Intel
SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX10.2, APX, AES-NI, SHA-NI, RDRAND, SM3, SM4, VT-x, VT-d Products, models, variants Brand name Core Ultra History
Nova_Lake_(microprocessor)
Random number generator
include their own high-speed hardware random number generators such as RDRAND. Instead, the data from the lava lamps is a secondary, independent source
Lavarand
64-bit extension of x86 architecture
extensions not concerned with general-purpose computation, including AES-NI and RDRAND, are excluded from the level requirements. On most recent x86_64 Linux distributions
X86-64
Intel microprocessor series released in 2026
x86-64 Extensions SSE4, AVX, AVX2, AVX-VNNI, AVX-IFMA AES-NI, SHA-NI, RDRAND, SM3, SM4 VT-x, VT-d P-core architecture Cougar Cove (P-cores) E-core architecture
Panther_Lake_(microprocessor)
CPU microarchitecture by Intel
RDRAND instruction, codenamed Bull Mountain. Changes over Sandy Bridge include: F16C (16-bit floating-point conversion instructions) extension RDRAND
Ivy Bridge (microarchitecture)
Ivy_Bridge_(microarchitecture)
Type of random number generator
metal. Mitigations include persisting a seed file across reboots, using RDRAND / RDSEED instructions where available, and querying a virtual hardware RNG
Non-physical true random number generator
Non-physical_true_random_number_generator
Instruction set extensions accelerating AES operations
Extensions (AVX) CLMUL instruction set FMA instruction set (FMA3, FMA4) RDRAND The instruction computes 4 parallel subexpressions of AES key expansion
AES_instruction_set
Probabilistic problem-solving algorithm
tested cryptographically secure pseudorandom numbers generated via Intel's RDRAND instruction set, as compared to those derived from algorithms, like the
Monte_Carlo_method
Brand of discontinued microprocessors produced by Intel
Boost, Intel vPro, Hyper-Threading are not available. Supports AES-NI and RDRAND. Integrated graphics are provided by Intel HD Graphics 510, utilizing a
Pentium
round keys used with the AESENC, AESENCLAST or AESDECLAST instructions. The RDRAND and RDSEED instructions may fail to obtain and return a random number if
List of x86 cryptographic instructions
List_of_x86_cryptographic_instructions
Instructions for the x86 microprocessors
PadLock (2003) AES-NI (2008); ARMv8 also has AES instructions CLMUL (2010) RDRAND (2012) SHA (2013) MPX (2015) SGX (2015) TDX (2021) Transactional memory
Advanced_Vector_Extensions
Trusted execution environment subsystem that runs on AMD microprocessors
manufacturing. The PSP also provides a random number generator for the RDRAND instruction and provides TPM services. The OEM/ODM can OTP fuse its PSB
AMD Platform Security Processor
AMD_Platform_Security_Processor
CPU microarchitecture
instruction set Supports Intel AESNI and PCLMUL instructions Supports Intel RDRAND and RDSEED instructions Supports Intel SHA extensions Supports Intel MPX
Goldmont_Plus
Microarchitecture by AMD
Excavator added hardware support for new instructions such as AVX2, BMI2 and RDRAND. Excavator is designed using High Density (aka "Thin") Libraries normally
Excavator_(microarchitecture)
Family of instruction set architectures
SSE2, NX bit, SMT, SSE3, SSSE3, SSE4.1, SSE4.2, AES-NI, CLMUL, SM3, SM4, RDRAND, SHA, MPX, SME, SGX, XOP, F16C, ADX, BMI, FMA, AVX, AVX2, AVX-VNNI, AVX-IFMA
X86
Intel microprocessor released in 2021
Instruction set x86 Instructions x86-16, IA-32, x86-64 Extensions AES-NI, CLMUL, RDRAND, SHA, TXT MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 AVX, AVX2, AVX-512
Rocket_Lake
/dev/random – Unix-like systems CryptGenRandom – Microsoft Windows Fortuna RDRAND instructions (called Intel Secure Key by Intel), available in Intel x86
List of random number generators
List_of_random_number_generators
Brand of microprocessors
SSE4.1, SSE4.2, AVX, AVX2, AVX-512 with Zen 4, FMA3, CVT16/F16C, ABM, BMI1, BMI2 AES, CLMUL, RDRAND, SHA, SME AMD-V, AMD-Vi History Predecessor Opteron
Threadripper
Eighth-generation Intel Core microprocessor family
Instruction set x86-64 Instructions x86-64 Extensions MMX, AES-NI, CLMUL, FMA3, RDRAND SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 AVX, AVX2, TXT, TSX, SGX VT-x, VT-d
Coffee_Lake
AMD brand for microprocessors
AVX2, AVX-512 with Zen 4, FMA3, CVT16/F16C, ABM, BMI1, BMI2 AES, CLMUL, RDRAND, SHA, SME AMD-V, AMD-Vi Variants Threadripper (high-end desktop and workstation)
Ryzen
provided. When using the HotSpot JVM OpenSSL RDRAND support is provided through the ENGINE interface. The RDRAND generator is not used by default. Based on
Comparison of cryptography libraries
Comparison_of_cryptography_libraries
Intel microprocessor family launched in 2019
Cove Instruction set x86-64 Instructions x86-64 Extensions AES-NI, CLMUL, RDRAND, SHA, TXT, SGX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
Ice_Lake_(microprocessor)
Intel microprocessor, released in 2024
SSE4.2 AVX, AVX2, FMA3, AVX-VNNI, AVX-IFMA, TSX VT-x, VT-d AES-NI, SHA, RDRAND E-core architecture Crestmont Cores Peak core clock Up to 3.2 GHz E-core
Sierra_Forest
Line of Intel microprocessors released in 2022
(E-cores) Instruction set x86 Instructions x86-64 Extensions AES-NI, CLMUL, RDRAND, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-VNNI
Raptor_Lake
Microprocessor family released in 2016
Instruction set x86-64 Instructions x86-64 Extensions MMX, AES-NI, CLMUL, FMA3, RDRAND SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 AVX, AVX2, TXT, TSX, SGX VT-x
Kaby_Lake
Extensions to the x86 instruction set architecture
PadLock (2003) AES-NI (2008); ARMv8 also has AES instructions CLMUL (2010) RDRAND (2012) SHA (2013) MPX (2015) SGX (2015) TDX (2021) Transactional memory
Advanced_Matrix_Extensions
Pseudorandom number generator file in Unix-like operating systems
phase timing jitter, hardware interrupt (timing assumed) are used. RDSEED/RDRAND is used on Intel-based Macs that support it. Seed (entropy) data is also
/dev/random
6th generation Xeon x86 server processors designed by Intel, released in 2024
architecture Instructions set x86 Instructions x86-64 Extensions AES-NI, CLMUL, RDRAND, SHA, TXT MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2,
Granite_Rapids
Line of Intel server and workstation processors
1, SSE4.2, AVX, AVX2, FMA3, AVX-512, AVX-VNNI, AMX, TSX, AES-NI, CLMUL, RDRAND Extensions SGX, SHA, TXT, VT-x, VT-d Products, models, variants Brand name
Xeon
Microprocessor brand name by Intel
IA-32, x86-64 (not for the N2xx and Z5xx series) Extensions AES-NI, CLMUL, RDRAND, SHA, TXT MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 AVX, AVX2, FMA3, AVX-VNNI
Intel_Atom
Intel processor family released in 2019
SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AES-NI, CLMUL, RDRAND TXT, SGX, VT-x, VT-d Products, models, variants Product code name CML Brand name
Comet_Lake
2024 Intel product line
Instructions x86, IA-32, x86-64 Extensions AES-NI, CLMUL, SM3, SM4, SHA, TXT, RDRAND, MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-VNNI
Arrow_Lake_(microprocessor)
AMD-V, AES, CLMUL, AVX, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND Two or Four CPU cores based on the Excavator microarchitecture L1 Cache:
List of AMD Opteron processors
List_of_AMD_Opteron_processors
Computing concept
enabled on motherboard Entropy from UEFI interface (if booted from UEFI) RDRAND CPU instruction if available Hardware system clock (RTC) OEM0 ACPI table
Entropy_(computing)
AMD brand of server microprocessors
(with Zen 4 and later), FMA3, CVT16/F16C, ABM, BMI1, BMI2, AES, CLMUL, RDRAND, SHA, SME, AMD-V, AMD-Vi Products, models, variants Core names Naples Rome
Epyc
Code name of a decryption program run by the NSA
News (2013-09-10). "Torvalds shoots down call to yank 'backdoored' Intel RdRand in Linux crypto". The Register. Tim Bray, Google Identity Team (July 2013)
Bullrun_(decryption_program)
CPU microarchitecture by Intel
Skylake Instruction set x86-16, IA-32, x86-64 Extensions AES-NI, CLMUL, RDRAND, MPX, TXT, SGX MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, ADX AVX
Skylake_(microarchitecture)
Extension to the x86 instruction set
PadLock (2003) AES-NI (2008); ARMv8 also has AES instructions CLMUL (2010) RDRAND (2012) SHA (2013) MPX (2015) SGX (2015) TDX (2021) Transactional memory
CLMUL_instruction_set
CPU microarchitecture used in Intel SoCs
instruction set Supports Intel AESNI and PCLMUL instructions Supports Intel RDRAND and RDSEED instructions Supports Intel SHA extensions Supports Intel MPX
Goldmont
Cryptographic device
material in lava lamps) List of random number generators Lottery machine RDRAND Trusted Platform Module Turan et al. 2018, p. 64. Schindler 2009, p. 7.
Hardware random number generator
Hardware_random_number_generator
Intel processor microarchitecture
Haswell Instruction set x86-16, IA-32, x86-64 Extensions AES-NI, CLMUL, RDRAND, TXT MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, FMA3, AVX, AVX2
Haswell_(microarchitecture)
Pseudorandom number generator
approximately twenty times faster than the hardware-implemented, processor-based RDRAND instruction set. However, the throughput is mediocre by modern standards
Mersenne_Twister
List of x86 microprocessor instructions
many/most x86 CPUs, while others are specific to a narrow range of CPUs. CLMUL RDRAND Advanced Vector Extensions 2 AVX-512 x86 Bit manipulation instruction set
List_of_x86_instructions
Type of standardized secure cryptoprocessors
stupid fTPM hwrnd thing." He said the CPU-based random number generation, rdrand, was equally suitable, despite having its share of bugs. In 2010, Christopher
Trusted_Platform_Module
Intel microprocessor, released in 2023
AVX, AVX2, FMA3, AVX-512, AVX-VNNI, TSX, AMX Extensions AES-NI, CLMUL, RDRAND, SHA, TXT, VT-x, VT-d Products, models, variants Product code name EMR Model
Emerald_Rapids
Series of microprocessors by AMD
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
AMD_APU
Line of discontinued microprocessors made by Intel
Windows XP and Vista. All Celerons of this generation added AES-NI and RDRAND instruction set. Similar to the Mendocino (Celeron-A): 250 nm, 32 KB L1
Celeron
CPU microarchitecture by Intel
(previously known as 10ESF) Instruction set x86, x86-64 Extensions AES-NI, CLMUL, RDRAND, SHA, TXT, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3
Golden_Cove
Computer instruction set introduced by AMD in 2009
PadLock (2003) AES-NI (2008); ARMv8 also has AES instructions CLMUL (2010) RDRAND (2012) SHA (2013) MPX (2015) SGX (2015) TDX (2021) Transactional memory
XOP_instruction_set
CPU socket for laptop AMD CPUs
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
Socket_FM2+
Intel microprocessor series released in 2023
E-cores) Instruction set x86-64 Instructions x86-64 Extensions AES-NI, CLMUL, RDRAND, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-VNNI
Meteor_Lake
Umbrella marketing term by Intel
Protection Technology Intel Identity Protection technology Intel Secure key (RDRAND) Intel Anti-Theft Technology Intel Boot Guard Intel OS Guard Intel Active
Intel_vPro
Architectural instruction
PadLock (2003) AES-NI (2008); ARMv8 also has AES instructions CLMUL (2010) RDRAND (2012) SHA (2013) MPX (2015) SGX (2015) TDX (2021) Transactional memory
F16C
Intel processor family
Instruction set x86-64 Instructions x86-64, Intel 64 Extensions MMX, AES-NI, CLMUL, RDRAND, FMA3, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX-512, SHA,
Cannon_Lake_(microprocessor)
Extension to the x86 instruction set
AES instruction set Block cipher mode of operation Intel SHA extensions RDRAND "VIA PadLock Programming Guide". August 4, 2005. Archived from the original
VIA_PadLock
Intel processor family (launched in 2019)
SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-512, Extensions AES-NI, CLMUL, RDRAND, MPX, TXT, TSX, VT-x, VT-d Products, models, variants Product code name
Cascade_Lake
Proposed extension to x86-64 instruction set architecture
PadLock (2003) AES-NI (2008); ARMv8 also has AES instructions CLMUL (2010) RDRAND (2012) SHA (2013) MPX (2015) SGX (2015) TDX (2021) Transactional memory
Advanced Synchronization Facility
Advanced_Synchronization_Facility
Instruction for x86 microprocessors
instructions to/from FP16 format 29 30 ia64 IA64 processor emulating x86 rdrnd RDRAND (on-chip random number generator) feature 30 31 pbe Pending Break Enable
CPUID
CPU socket for AMD CPUs
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
Socket_FT1
American electronics company
followed up with specifications AES-NI, Intel SHA extensions in 2013, and RDRAND in 2015.[citation needed] Because memory performance is the limiting factor
Centaur_Technology
Intel microprocessor, released in 2023
1, SSE4.2, AVX, AVX2, FMA3, AVX-512, AVX-VNNI, TSX, AMX, AES-NI, CLMUL, RDRAND, UINTR Extensions SHA, TXT, VT-x, VT-d, DSA, QAT, DLB, IAA Products, models
Sapphire_Rapids
Intel microprocessor family
(E-cores) Instruction set x86 Instructions x86-64 Extensions AES-NI, CLMUL, RDRAND, SHA, TXT, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3
Alder_Lake
Fifth generation of Intel Core processors
SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, TSX, FMA3 AES-NI, CLMUL, RDRAND, TXT VT-x, VT-d Products, models, variants Product code name Rockwell Brand name
Broadwell_(microarchitecture)
Intel microprocessor, released in 2018
Instruction set x86-16, IA-32, x86-64 Extensions MMX, AES-NI, CLMUL, FMA3, RDRAND SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 AVX, AVX2, TXT, TSX, SGX VT-x, VT-d
Whiskey_Lake
CPU microarchitecture by Intel
SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-VNNI, AES-NI, CLMUL, RDRAND, SHA, TXT, VT-d, VT-x Products, models, variants Product code names Alder
Gracemont_(microarchitecture)
x87) SIMD (MMX, SSE, AVX, FMA, AMX) Virtualization (VT-x, AMD-V, TDX) Cryptographic (e.g. RDRAND, AES-NI) Discontinued (e.g. 3DNow!, MPX, XOP) v t e
List_of_x86_SIMD_instructions
Intel microprocessor family, released in 2020
1, SSE4.2, AVX, AVX2, FMA3, AVX-512, bfloat16 Extensions AES-NI, CLMUL, RDRAND, TXT, FSGSBASE, MOVBE, F16C, BMI, BMI2, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT
Cooper_Lake_(microprocessor)
"integer performance is essentially identical, however the floating point and RDRAND and RDSEED instructions' performance has been reduced" from the equivalent
AMD–Chinese_joint_venture
Chinese semiconductor chip manufacturer
KH-30000 (server) 2019 16 nm 8 (up to) 3 GHz (up to) DDR4 PCIe 3.0 RDSEED, RDRAND, SHA, UMIP supported SoC Manufactured by TSMC Lujiazui KX-6000G (consumer)
Zhaoxin
PadLock (2003) AES-NI (2008); ARMv8 also has AES instructions CLMUL (2010) RDRAND (2012) SHA (2013) MPX (2015) SGX (2015) TDX (2021) Transactional memory
SSE5
CPU microarchitecture by Intel
10 nm SuperFin (10SF) Instruction set x86-64 Extensions AES-NI, CLMUL, RDRAND, SHA, TXT, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX-512
Willow_Cove
AMD's dedicated video decoding ASIC
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
Unified_Video_Decoder
Cryptographic algorithm for random number generation
procedure provides the seed from seed files, external entropy, TPM randomness, RDRAND/RDSEED instructions, ACPI-OEM0 table, UEFI entropy, and the current time
CryptGenRandom
Intel microprocessor family
Cove Instruction set x86-64 Instructions x86-64 Extensions AES-NI, CLMUL, RDRAND, SHA, TXT, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX-512
Tiger_Lake
Intel CPU microarchitecture launched in 2019
10 nm FinFET process Instruction set x86, x86-64 Extensions AES-NI, CLMUL, RDRAND, SHA, TXT, SGX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
Sunny Cove (microarchitecture)
Sunny_Cove_(microarchitecture)
x87) SIMD (MMX, SSE, AVX, FMA, AMX) Virtualization (VT-x, AMD-V, TDX) Cryptographic (e.g. RDRAND, AES-NI) Discontinued (e.g. 3DNow!, MPX, XOP) v t e
List of x86 virtualization instructions
List_of_x86_virtualization_instructions
Extension to the x86 instruction set
PadLock (2003) AES-NI (2008); ARMv8 also has AES instructions CLMUL (2010) RDRAND (2012) SHA (2013) MPX (2015) SGX (2015) TDX (2021) Transactional memory
FMA_instruction_set
CPU microarchitecture
x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 AES-NI, RDRAND, CLMUL, SHA VT-x, VT-d Products, models, variants Model Pentium Celeron
Tremont_(microarchitecture)
AMD hardware accelerator for encoding MP4 H.264 videos, built into AMD GPU's
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
Video_Coding_Engine
Microarchitecture by AMD
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
Steamroller (microarchitecture)
Steamroller_(microarchitecture)
Computing system
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
Heterogeneous System Architecture
Heterogeneous_System_Architecture
CPU socket for AMD CPUs
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
Socket_FM2
C++ software library
number generators LCG, KDF2, Blum Blum Shub, ANSI X9.17, Mersenne Twister, RDRAND and RDSEED High speed stream ciphers ChaCha8/12/20, ChaCha20 (IETF version)
Crypto++
Microarchitecture from Intel
x86-64 Extensions MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 AES-NI, RDRAND, CLMUL VT-x Products, models, variants Brand names Atom Celeron Pentium
Silvermont
X86 assembler
supplement MOVD. Remaining instructions added in 2.16. Random Number Generator: RDRAND, RDSEED added in 2.13. half-precision conversions: F16C (VCVTPH2PS, VCVTPS2PH)
Open_Watcom_Assembler
Topics referred to by the same term
(instruction), code name for Intel's hardware random number generator and for the RdRand instruction it feeds Bull Mountain, a novel by the American Brian Panowich
Bull_Mountain
CPU socket for laptop AMD CPUs
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
Socket_FP3
x87) SIMD (MMX, SSE, AVX, FMA, AMX) Virtualization (VT-x, AMD-V, TDX) Cryptographic (e.g. RDRAND, AES-NI) Discontinued (e.g. 3DNow!, MPX, XOP) v t e
List of discontinued x86 instructions
List_of_discontinued_x86_instructions
CPU socket for AMD CPUs
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
Socket_FM1
Brand name by AMD
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
AMD_PowerPlay
CPU socket for laptop AMD CPUs
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
Socket_FT3
Brand of AMD video card products
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
AMD_Eyefinity
CPU socket for laptop AMD CPUs
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
Socket_FS1
CPU socket for laptop AMD CPUs
—N/a v2 v1 v2 BMI1, AES-NI, CLMUL, and F16C —N/a MOVBE —N/a AVIC, BMI2, RDRAND, and MWAITX/MONITORX —N/a SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC
Socket_FP2
RDRAND
RDRAND
RDRAND
RDRAND
Surname or Lastname
English
English : unexplained. Compare Minnie.
Surname or Lastname
English
English : occupational name, probably for a goatherd (from Middle English kid(e) ‘young goat’ + man ‘man’), but possibly also for a cutter of faggots (from Middle English kidde ‘faggot’).
Girl/Female
Scandinavian
Abbreviation of Katherine. Pure.
Girl/Female
Muslim
The one who brings happiness
Girl/Female
Hindu, Indian
Queen of Beauty
Boy/Male
British, English
From the Church's Meadow
Girl/Female
Tamil
Gayatry | கயாதà¯à®°à¯à®¯
Gayathry Mantra, Mother of the Vedas or Goddess Saraswati
Girl/Female
Hebrew American Spanish
Star.
Girl/Female
Hindu
Gift from God, Victorious
Boy/Male
English Teutonic
noble.
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