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Topics referred to by the same term
Condition code can refer to: Condition code register, in computing Uncertainty parameter, in astronomy This disambiguation page lists articles associated
Condition_code
CPU register containing flags
central processing unit (CPU), a status register, flag register, or condition code register (CCR) is a register that stores flags (bits) indicating the
Status_register
Field Condition report that allows pilots to assess braking action when the runway is not dry. TALPA assessment generates a Runway Condition Code (RWYCC)
Takeoff and Landing Performance Assessment
Takeoff_and_Landing_Performance_Assessment
that could impede their driving capability. They are then assigned a condition code(s) if they fall within a category. *Note: Special driving conditions
Driving license in the Philippines
Driving_license_in_the_Philippines
Internet error message
generates a web page for the condition and the client displays it, and often the content indicates the error code. Since the condition is relatively commonly-encountered
HTTP_404
Instruction set architecture developed by Digital Equipment Corporation
that set or cleared, respectively, all four condition codes. Clearing or setting none of the condition codes (opcodes 000240 and 000260, respectively) could
PDP-11_architecture
Set of codewords, none a prefix of another
necessarily a prefix code. Prefix codes are also known as prefix-free codes, prefix condition codes and instantaneous codes. Although Huffman coding is just one
Prefix_code
Microprocessor
the condition code register (CCR), and modification of it is not privileged. The 68000 comparison, arithmetic, and logic operations modify condition codes
Motorola_68000
Computer processor element
four condition code values, 23 + 22 + 21 + 20. (Since IBM uses big-endian bit numbering, mask value 8 selects code 0, mask value 4 selects code 1, mask
Program_status_word
Safety of operations on aircraft runways
(TALPA) was introduced in 2016, whereby airport operators report Runway Condition Codes (RWYCC) for take-off and landing. Index of aviation articles Runway
Runway_safety
RISC instruction set architecture
BVS (overflow set). The FPU and CP have sets of condition codes separate from the integer condition codes and from each other; two additional sets of branch
SPARC
64-bit RISC instruction set architecture
(BWX)) The Alpha does not have condition codes for integer instructions to remove a potential bottleneck at the condition status register. Instructions
DEC_Alpha
Machine instruction that indicates to a computer to do nothing
((void)0). Similar techniques can be used by user code; for instance, consider the following code that defines a macro over the prefetch builtin function
NOP_(code)
When a system's behavior depends on timing of uncontrollable events
race condition can arise in software when a computer program has multiple code paths that are executing at the same time. If the multiple code paths
Race_condition
Classification of radio frequency signals
currently used in amateur radio. This is often but not necessarily Morse code. A2A Signalling by transmitting a modulated tone with a carrier, so that
Types_of_radio_emissions
Cooling of air in an enclosed space
Air conditioning, often abbreviated as A/C (US) or air con (UK), is the process of removing heat from an enclosed space to achieve a more comfortable interior
Air_conditioning
Parameter introduced by the Minor Planet Center
larger the uncertainty. The uncertainty parameter is also known as condition code in JPL's Small-Body Database Browser. The U value should not be used
Uncertainty_parameter
Code coverage criterion
Modified condition/decision coverage (MC/DC) is a code coverage criterion used in software testing. MC/DC requires all of the below during testing: Each
Modified condition/decision coverage
Modified_condition/decision_coverage
Type of microcontroller register
or branch to modify the program counter. For another example, the condition code register might not be directly writable, instead being updated only
Special_function_register
Model independent architecture for the S/360 line of mainframe computers
other things) the address of the current instruction being executed, condition code and interrupt masks. Load Program Status Word (LPSW) is a privileged
IBM_System/360_architecture
Family of RISC-based computer architectures
Technical Reference Manual r0p4. Retrieved 3 July 2026. "Condition Codes 1: Condition flags and codes". ARM Community. 11 September 2013. Retrieved 26 September
ARM_architecture_family
Series of 32 bit CISC microprocessors
the condition code register (CCR), and modification of it is not privileged. The 68000 comparison, arithmetic, and logic operations modify condition codes
Motorola_68000_series
Microcontroller
16-bit stack pointer SP, a 16-bit program counter PC, and an 8-bit condition code register CCR. Some instructions refer to the different bytes in the
Motorola_68HC08
lists standard and notable non-standard HTTP response status codes. Standardized codes are defined by IETF as documented in Request for Comments (RFC)
List_of_HTTP_status_codes
Form of conditionals in computer programming
that have comprehensive Condition Codes generated by instructions may reduce code size further by directly using the Condition Registers in or as predication
Predication (computer architecture)
Predication_(computer_architecture)
Self-synchronizing line code
other names, including biphase mark code (BMC), F2F (frequency/double frequency), Aiken biphase, and conditioned diphase. Differential Manchester encoding
Differential Manchester encoding
Differential_Manchester_encoding
Coding guidelines by Gerald J. Holzmann
Reliable Software. The rules are intended to eliminate certain C coding practices that make code difficult to review or statically analyze. These rules are
The Power of 10: Rules for Developing Safety-Critical Code
The_Power_of_10:_Rules_for_Developing_Safety-Critical_Code
Metric for source code testing
condition coverage does not necessarily imply branch coverage. For example, consider the following Pascal code fragment: if a and b then Condition coverage
Code_coverage
Of a function, an additional effect besides returning a value
side effect is an arithmetic instruction that implicitly modifies condition codes (a hidden side effect) while it explicitly modifies a register (the
Side effect (computer science)
Side_effect_(computer_science)
Series of 8-bit microcontrollers
significant bits hardwired to 1, a 13-bit program counter PC, and an 8-bit condition code register CCR. Among the HC05's there are several processor families
Motorola_68HC05
One's current state of health, usually within a hospital
patient's condition. Each National Health Service (NHS) trust has its own guidance for statements to the press. The Department of Health's code of practice
Medical_state
Instruction in computer program
an IF-THEN statement specifying the condition(s). All high level languages support algorithms that can re-use code as a loop, a control structure that
Branch_(computer_science)
Capabilities of a computer architecture
a new MOVE from CCR instruction was provided to allow access to the condition code register only. The IA-32 instruction set of the Pentium processor contains
Popek and Goldberg virtualization requirements
Popek_and_Goldberg_virtualization_requirements
8-bit microcontroller family
accumulators, A and B, two sixteen-bit index registers, X and Y, a condition code register, a 16-bit stack pointer, and a program counter. In addition
Motorola_68HC11
American semiconductor design company
The optimizer then eliminates common sub-expressions and unnecessary condition code operations and, potentially, applies other optimizations such as loop
Transmeta
Technology of indoor and vehicular environmental comfort
Air-conditioning and Refrigeration Distributors International), ASHRAE, SMACNA, ACCA (Air Conditioning Contractors of America), Uniform Mechanical Code,
Heating, ventilation, and air conditioning
Heating,_ventilation,_and_air_conditioning
Topics referred to by the same term
Coordination Runtime, from the Microsoft Robotics Developer Studio Condition Code Register, or status register, in computer processor architecture Constant
CCR
Control flow construct for executing code repeatedly
two parts: a condition and a body. The condition is a logical statement depending on the state of the program and the body is a block of code that runs as
Loop_(statement)
Set of rules defining correctly structured programs
if/elseif statement is as follows: if (condition): // code here elseif (condition): // code here else: // code here endif; This style is sometimes called
PHP_syntax_and_semantics
Alert posture used by the United States Armed Forces
The defense readiness condition (DEFCON) is an alert state used by the United States Armed Forces. The DEFCON system was developed in 1959 by the Joint
DEFCON
Open-source CPU instruction set architecture
take more code space. Designers planned to reduce code size with library routines to save and restore registers. RISC-V has no condition code register
RISC-V
Computer architecture
The meaning of various flag bits (such as S=1 enables setting the condition codes) is identical to the ARM instruction set. The load/store multiple instruction
Unicore
is to obfuscate any traced encrypted code. Its decryption process is affected by the contents of the condition code register (CCR). For example, an arithmetic
Trace_vector_decoder
proof-carrying code). VC generators are often coupled with SMT solvers in the backend of a program verifier. After a verification condition generator has
Verification condition generator
Verification_condition_generator
Register, store certain status information, the instruction length code, the condition code and the program mask, in the top byte of the return address. A
IBM_System/370-XA
Intentional withholding of information
A code of silence is a condition in effect when a person opts to withhold what is believed to be vital or important information voluntarily or involuntarily
Code_of_silence
Model that describes the programmable interface of a computer processor
registers, placing the result in a register, possibly setting one or more condition codes in a status register. increment, decrement in some ISAs, saving operand
Instruction_set_architecture
Series of microarchitectures and instruction set architecture by AMD
LLVM has code generation support for all GCN variants. Mesa uses the Mesa-internal ACO compiler for GCN code generation. GCC implements code generation
Graphics_Core_Next
Assembly languages for IBM System/360 and successor mainframes
instruction mnemonics are BALR for a call storing the return address and condition code in a register, SVC, DIAG, and ZAP. System/360 machine instructions are
IBM Basic assembly language and successors
IBM_Basic_assembly_language_and_successors
Phrases used over a public address system
Hospital emergency codes are coded messages often announced over a public address system of a hospital to alert staff to various classes of on-site emergencies
Hospital_emergency_codes
Computer programming problem of nested checks
source code. One way is to check each condition in turn and if a condition fails, return from the subroutine at that point, indicating an error condition exists
Pyramid_of_doom_(programming)
Telecommunications coding technique
telecommunications, a non-return-to-zero (NRZ) line code is a binary code in which ones are represented by one significant condition, usually a positive voltage, while
Non-return-to-zero
Microprocessor produced by Western Digital
← R0 The four condition codes in the processor status word (PSW) are N indicating a negative value Z indicating a zero (equal) condition V indicating an
WD16
Instruction set architecture
parallelism. To alleviate the bottleneck caused by a single condition bit, seven condition code bits were added to the floating-point control and status
MIPS_architecture
International standard for financial transaction card originated interchange messaging
Messages, data elements, and code values Part 2: Application and registration procedures for Institution Identification Codes (IIC) Part 3: Maintenance procedures
ISO_8583
Hypothetical computer by Donald Knuth
and the operation code (1 byte). All operation codes have an associated mnemonic. MIX programs frequently use self-modifying code, in particular to return
MIX_(abstract_machine)
Type of SCSI error code
Key Code Qualifier is an error-code returned by a SCSI device. When a SCSI target device returns a check condition in response to a command, the initiator
Key_Code_Qualifier
Multi-chip CPU by IBM implementing the POWER instruction set architecture
branch processing unit (BPU). The BPU contains the program counter, the condition code register and a loop register. The ICU contains 0.75 million transistors
POWER1
Job control language for IBM mainframes
problems, do not use the results! OS JCL refers to the return code as COND ("condition code"), and can use it to decide whether to run subsequent steps
Job_Control_Language
Code that indicates the nature of an error
an anomalous condition. Error codes reported by consumer electronics are used to help diagnose and repair technical problems. An error code can be communicated
Error_code
Wall-mounted air conditioning system
terminal air conditioner"". Code of Federal Regulations. U.S. Department of Energy. Retrieved 18 October 2023. "Room-size Air Conditioner Fits Under Window
Packaged terminal air conditioner
Packaged_terminal_air_conditioner
Topics referred to by the same term
Undefined behavior, computer code whose behavior is not specified under certain conditions Undefined value, a condition where an expression does not have
Undefined
Computer instruction set architecture
registers (VRs) as part of the VSRs for vector operations. 8 × 4-bit condition register fields (CRs) for comparison and control flow. 11 special registers
Power_ISA
Aspect of the instruction set architecture of CPUs
such as a 'compare' is used to set a condition code, and subsequent instructions include a test on that condition code to see whether they are obeyed or
Addressing_mode
Line of computers sold by Digital Equipment Corporation
available memory while still being compatible with unmodified user mode PDP-11 code. The name "VAX-11", used on early models, was chosen to highlight this capability
VAX
Laptop computer released by Epson in 1981
are:[citation needed] A (Accumulator A) B (Accumulator B) X (Index Register) C (Condition Code Register) S (Stack Pointer) P (program counter) The monitor can be used
Epson_HX-20
Set of rules for a one-on-one combat
A code duello is a set of rules for a one-on-one combat, or duel. Codes duello regulate dueling and thus help prevent vendettas between families and other
Code_duello
How software progresses through its implementation
Jumps to a label based on a condition; a high-level programming statement that closely mimics a similar used machine code instruction if-then Rather than
Control_flow
8-bit microcontroller family
accumulator A and the stack pointer remain 8 and 16 bits, respectively. The condition code register has two more defined bits, for a total of seven. There is an
STM8
condition not listed above] (coded 294.1 in the DSM-IV) 294.8 Dementia NOS 294.0 Amnestic disorder due to... [indicate the general medical condition]
List of mental disorders in the DSM-IV and DSM-IV-TR
List_of_mental_disorders_in_the_DSM-IV_and_DSM-IV-TR
2003 novel by Dan Brown
The Da Vinci Code is a 2003 mystery thriller novel by Dan Brown. It is one of the best-selling American novels of all time. Brown's second novel to include
The_Da_Vinci_Code
Persistent human health condition or disease
those studying the United States, utilize the Chronic Condition Indicator (CCI) which maps ICD codes as "chronic" or "non-chronic". The list below includes
Chronic_condition
Hitachi variant of the Motorola 6809 8-bit microprocessor
zero and writes to it are ignored. Mode register 'MD', a secondary Condition Code register that controls the operating mode. Only 4 bits of this register
Hitachi_6309
Status register of x86 architecture
flag(s) within FLAGS register value. All FLAGS registers contain the condition codes, flag bits that let the results of one machine-language instruction
FLAGS_register
Combinational digital circuit
multi-bit register, which is referred to as the "status register" or "condition code register". Depending on the ALU operation being performed, some status
Arithmetic_logic_unit
8-bit microprocessor
capability; a 14-bit program counter; a seven-level, 14-bit call stack; four condition code bits: carry (C), even parity (P), zero (Z), and sign (S). The 8008 was
Intel_8008
Line of microcontrollers manufactured by Freescale Semiconductor
and Y, a 16-bit program counter, a 16-bit stack pointer and an 8-bit Condition Code Register. Unlike the 68HC11 the processor has 16bit internal data paths
Motorola_68HC12
Unique numeric book identifier since 1970
(International Standard Recording Code) ISTC (International Standard Text Code) ISWC (International Standard Musical Work Code) ISSN (International Standard
ISBN
4-bit microprocessor
the exclusivity agreement. In May 1971, Busicom agreed to this, on the condition that it not be used for any other calculator project and that Intel would
Intel_4004
Changing between languages during a conversation
In linguistics, code-switching or language alternation is the process of shifting from one linguistic code (a language or dialect) to another, depending
Code-switching
Internet top-level domain generally used by or reserved for a country
A country code top-level domain (ccTLD) is an internet top-level domain generally used or reserved for a country, sovereign state, or dependent territory
Country_code_top-level_domain
16-bit microprocessor
I/O port space. The 8086 has a 16-bit flags register. Nine of these condition code flags are active, and indicate the current state of the processor: Carry
Intel_8086
Equity of condition in tax law and governmental spending is the economic condition, often arbitrary, that political leaders believe a person should be
Equity_of_condition
Instruction for x86 processors
register. There are 8 variants of the instruction selected by the condition codes that need be set for the instruction to perform the move. Similar to
FCMOV
Instruction set architecture extension for microprocessors
bits. EVEX prefix for conditional CMP and TEST: SC bits are source condition code (SCC). OF, SF, ZF, CF are overflow, sign, zero, and carry flags to test
EVEX_prefix
Classification system
for structural steels, category 1 - Sxxx. Example : S355J2 Delivery condition codes are also relatively common, the most common being: Example : S355J2+N
Steel_grades
8-bit microcontroller family
lower half, X, is used in isolation by 6805-compatible instructions), a condition code register, a 16-bit stack pointer, and a program counter. For compatibility
Motorola_S08
Brevity codes used by a variety of US professionals
transmissions. The police version of ten-codes is officially known as the APCO Project 14 Aural Brevity Code. The codes, developed during 1937–1940 and expanded
Ten-code
Early transistor computer
Previous Result Indicators (PRIs) - what would now be called the Status or Condition code register. A three bit register holding information about the result
RCA_501
Entropy encoding
obtain a set of codes of certain length, you have to start with the boundary condition usually 0....0 for the largest and last code and work upwards
Unary_coding
Hybrid RISC digital signal processor
DAGs (data address generators) are designed to assist in writing efficient code requiring fewer instructions. Other applications use the RISC features, which
Blackfin
Type of computer instructions
vector population count vpopct Vector test under mask vtm - sets a Condition Code based on comparing all elements of one register against a second vector
Bit_manipulation_instructions
Computer processor which works on arrays of several numbers at once
register and update a Condition Code that the Branch could test. In effect VLVCU combined two (three if including Condition Code setting) into one: # IBM
Vector_processor
Object or module in concurrent programming
mutex used by one or more condition variables (one or more monitors) may also be shared with code that does not use condition variables (and which simply
Monitor_(synchronization)
American work authorization document
The Labor Condition Application (LCA) is an application filed by prospective employers on behalf of workers applying for work authorization for the non-immigrant
Labor_Condition_Application
Approach for designing software
programming provides a certain functionality, it may: Expect a certain condition to be guaranteed on entry by any client module that calls it: the method's
Design_by_contract
processors. RS08 interrupts can wake the processor from a WAIT or STOP condition (where execution is temporarily halted), but otherwise do not change program
Freescale_RS08
Theoretical computer used for teaching
specified branch condition is satisfied. If the branch condition fails, execution continues with the next instruction in ROM. Mnemonic codes are provided
Hack_computer
Line code in which the signal value returns to zero between each pulse
Return-to-zero (RZ or RTZ) describes a line code used in telecommunications signals in which the signal drops (returns) to zero between pulses. This takes
Return-to-zero
ventilation, and air conditioning) Plumbing Electrical systems Vertical transportation (elevators and escalators) Life safety, ADA, code compliance, air quality
Property_condition_assessment
travel, tourism, insurance
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travel, tourism, insurance