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The MultiProcessor Specification (MPS) for the x86 architecture is an open standard describing enhancements to both operating systems and firmware, which
MultiProcessor_Specification
Computer firmware interface standard
Advanced Power Management (APM), the MultiProcessor Specification, and the Plug and Play BIOS (PnP) Specification. ACPI brings power management under the
ACPI
Family of computer interrupt controllers
construction of multiprocessor systems. It is one of several architectural designs intended to solve interrupt routing efficiency issues in multiprocessor computer
Advanced Programmable Interrupt Controller
Advanced_Programmable_Interrupt_Controller
Topics referred to by the same term
used to describe mathematical programming problems MultiProcessor Specification, Intel specification for multi-processor computers of x86 architecture
MPS
Firmware for hardware initialization and OS runtime services
Management Interface (DMI), VESA BIOS Extensions (VBE), e820 and MultiProcessor Specification (MPS). Starting from the year 2000, most BIOSes provide ACPI
BIOS
Micro-electronic component
than general-purpose instructions for a specific type of workload. Multiprocessor SoCs have more than one processor core by definition. The Arm architecture
System_on_a_chip
GPU microarchitecture designed by Nvidia
the Turing and Ampere microarchitectures, featuring a new streaming multiprocessor, a faster memory subsystem, and a transformer acceleration engine. The
Hopper_(microarchitecture)
Mathematical program specifications
science, formal methods are mathematically rigorous techniques for the specification, development, analysis, and verification of software and hardware systems
Formal_methods
Interface Specification 5.0" (PDF). Archived from the original (PDF) on September 14, 2012. Retrieved December 6, 2011. "BIOS Boot Specification version
List_of_computer_standards
GPU microarchitecture designed by Nvidia
Learning". arXiv:2310.10537 [cs.LG]. "OCP Microscaling Formats (MX) v1.0 Specification". Open Compute Project. 2024. Retrieved February 5, 2025. "OpenAI Triton
Blackwell_(microarchitecture)
and no replacement specification is listed, either the specification was withdrawn without replacement or a replacement specification could not be identified
List_of_DIN_standards
processors. IBM however developed their Multiprocessor Interrupt Controller (MPIC) based on the OpenPIC register specification. In the reference IBM design, the
OpenPIC_and_MPIC
Universal computer bus standard
Bus Specifications for Multiprocessor Architectures: Futurebus+, IEEE Std 896.1-1987 IEEE Standard for Futurebus+(R) -- Logical Protocol Specification, IEEE
Futurebus
Motherboard form factor specification
motherboard form factor specification introduced by Intel at the IDF in September 1998, for its use at high-end, multiprocessor, multiple-hard-disk servers
WTX_(form_factor)
Parallel computing platform and programming model
Retrieved 2024-07-27. "Specifications | oneAPI". oneAPI.io. Retrieved 2024-07-27. "oneAPI Specification – oneAPI Specification 1.3-rev-1 documentation"
CUDA
Programming abstraction
threads. The threads in the same thread block run on the same stream multiprocessor. Threads in the same block can communicate with each other via shared
Thread block (CUDA programming)
Thread_block_(CUDA_programming)
Formal specification language
model checker for TLA+ specifications; TLC was used to find errors in the cache coherence protocol for a Compaq multiprocessor. Lamport published a full
TLA+
Computer memory that can be accessed by multiple processes
accessed by several different central processing units (CPUs) in a multiprocessor computer system. Shared memory systems may use: uniform memory access
Shared_memory
Advanced Power Management (APM), the MultiProcessor Specification, and the Plug and Play BIOS (PnP) Specification. Internally, ACPI advertises the available
History_of_personal_computers
processing units (GPUs) and video cards from Nvidia, based on official specifications. In addition some Nvidia motherboards come with integrated onboard GPUs
List of Nvidia graphics processing units
List_of_Nvidia_graphics_processing_units
Computer processor interconnection technology first introduced in 2001
microprocessors. Another use for HyperTransport is as an interconnect for NUMA multiprocessor computers. AMD used HyperTransport with a proprietary cache coherency
HyperTransport
Microprocessor with more than one processing unit
typically integrate the cores onto a single IC die, known as a chip multiprocessor (CMP), or onto multiple dies in a single chip package. As of 2024, the
Multi-core_processor
GPU microarchitecture by Nvidia
3 stereoscopic/3D displays (NV Surround) Next Generation Streaming Multiprocessor (SMX) Polymorph-Engine 2.0 Simplified Instruction Scheduler Bindless
Kepler_(microarchitecture)
Equivalence of all cached copies of a memory location
its own local cache of a shared memory resource. In a shared memory multiprocessor system with a separate cache memory for each processor, it is possible
Cache_coherence
GPU microarchitecture by Nvidia
GP100 architecture include the following: In Pascal, a SM (streaming multiprocessor) consists of between 64-128 CUDA cores, depending on if it is GP100
Pascal_(microarchitecture)
Real-time operating system
Real-Time Executive for Multiprocessor Systems (RTEMS), formerly Real-Time Executive for Missile Systems, and then Real-Time Executive for Military Systems
RTEMS
multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output
List of Intel graphics processing units
List_of_Intel_graphics_processing_units
Interactive theorem proving systems
Peter Sewell; Francesco Zappa Nardelli. The Semantics of Power and ARM Multiprocessor Machine Code (PDF). DAMP 2009. pp. 13–24. Gordon, Michael J. C. (1996)
HOL_(proof_assistant)
Specialized electronic circuit that accelerates graphics
memory caches. Performance is also affected by the number of streaming multiprocessors (SM) for NVidia GPUs, or compute units (CU) for AMD GPUs, or Xe cores
Graphics_processing_unit
demand; facilitate compiling for non-sequential program execution in multiprocessor environments. Scholz, Sven-Bodo (1996). Single Assignment C – Entwurf
SAC_programming_language
lightweight threads designed for use on shared memory multiprocessors (such as SMPs). The Nano-threads specification was written in 1997. X Martorell; J Labarta;
Nano-threads
Intel CPU edge connector specification
multiprocessing (SMP) markets. The Pentium II Xeon, which was aimed at multiprocessor workstations and servers, was largely similar to the ordinary Pentium
Slot_2
Canadian computer scientist (born 1955)
Advisor. Cs.cmu.edu. Retrieved on 2013-07-17. James Gosling mentioned a multiprocessor Unix in his statement during the US vs Microsoft Antitrust DOJ trial
James_Gosling
Standards for connecting components of a computer
single-board computers (based on both Intel and PowerPC architectures), multiprocessors, graphics processors, FPGA-based processing modules, mass storage,
VPX
Series of GPUs by Nvidia
3 stereoscopic/3D displays (NV Surround) Next Generation Streaming Multiprocessor (SMX) A New Instruction Scheduler Bindless Textures CUDA Compute Capability
GeForce_600_series
Data structure that can be used by multiple threads
synchronization operations (see synchronization primitives) available on modern multiprocessor machines that allow multiple threads to reach consensus. This consensus
Concurrent_data_structure
CPU instruction to increment a value in memory by a given amount
disable interrupts before accessing a critical section. However, in multiprocessor systems (even with interrupts disabled) two or more processors could
Fetch-and-add
Interaction of threads in Java software
processor and the memory subsystem to achieve maximum performance. On multiprocessor architectures, individual processors may have their own local caches
Java_memory_model
Professional. p. 906. ISBN 978-0-321-15630-3. Device Control Register Bus 3.5 Architecture Specifications IBM Multiprocessor Interrupt Controller. Data Book
Device_control_register
Computer operating system
6.3 was released for the SGI O2 workstation only. IRIX 6.4 improved multiprocessor scalability for the Octane, Origin 2000, and Onyx2 systems. The Origin
IRIX
Series of GPUs by Nvidia
Texture mapping units: Render output units The number of streaming multiprocessors on the GPU. GTX 1060 and GTX 1080 cards shipped after April 2017 feature
GeForce_10_series
American computer engineer (born 1958/1959)
x86-64 instruction set and HyperTransport interconnect, mainly used for multiprocessor communications. In 1999, he left AMD to work at SiByte to design MIPS-based
Jim_Keller_(engineer)
GPU microarchitecture by Nvidia
MTr/mm2 118.9 MTr/mm2 Graphics processing clusters 12 7 5 3 2 Streaming multiprocessors 144 80 60 36 24 CUDA cores 18432 10240 7680 4608 3072 Texture mapping
Ada Lovelace (microarchitecture)
Ada_Lovelace_(microarchitecture)
Computer synchronizing instruction
includes synchronization primitives and lock-free data structures on multiprocessor systems, and device drivers that communicate with computer hardware
Memory_barrier
Executing several computations during overlapping time periods
applies them to memory accesses. Concurrent programming languages and multiprocessor programs must have a consistency model (also known as a memory model)
Concurrent_computing
Overclocking technology by Intel
"Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System". 2009 18th International Conference on Parallel Architectures
Intel_Turbo_Boost
Open-source CPU instruction set architecture
as x86 and ARM, RISC-V is described as "free and open" because its specifications are released under permissive open-source licenses and can be implemented
RISC-V
Chinese artificial intelligence company
overlapping computation and communication, such as dedicating 20 streaming multiprocessors out of 132 per H800 for only inter-GPU communication. They lowered
DeepSeek
Sixth-generation x86 microprocessor by Intel
CPU an advantage in input/output performance over older x86 CPUs. In multiprocessor configurations, Pentium Pro's integrated cache skyrocketed performance
Pentium_Pro
Series of GPUs by Nvidia
bit on GM107, further saving power. Nvidia also changed the streaming multiprocessor design from that of Kepler (SMX), naming it SMM. The structure of the
GeForce_900_series
Nvidia's line of general purpose GPUs
render output units : tensor cores : ray-tracing cores (streaming multiprocessors) GPU Boost is a default feature that increases the core clock rate
Nvidia_Tesla
Model of IBM mainframe specially designed for use in air traffic control
The IBM 9020 was an IBM System/360 computer adapted into a multiprocessor system for use by the U.S. FAA for Air Traffic Control. Systems were installed
IBM_9020
8-bit microprocessor
several processors to share a common memory bus in a daisy-chained multiprocessor arrangement, or to support direct memory access hardware. The SC/MP
National_Semiconductor_SC/MP
High-speed interconnect standard for shared memory multiprocessing and message passing
and a simple interface; i.e. a standard to replace existing buses in multiprocessor systems with one with no inherent scalability and performance limitations
Scalable_Coherent_Interface
32-bit CPU for the Wii U
PowerPC 750 based, but enhanced with larger and faster caches and multiprocessor support. Rumors that the Wii U CPU was derived from IBM's high-end POWER7
Espresso_(processor)
CPU instructions which read and modify an unaltered value in memory
originally proposed by Jensen, Hagensen, and Broughton for the S-1 AAP multiprocessor[failed verification] at Lawrence Livermore National Laboratory. If any
Load-link/store-conditional
Microarchitecture from Intel
cores have been used in Knights Landing versions of Intel's Xeon Phi multiprocessor HPC chips, with changes for HPC including AVX-512 vector units. Intel
Silvermont
American computing vendor
on the Concurrent platform. Optimizing Fortran for a shared-memory multiprocessor presented special issues regarding do loops and cache thrashing, a subject
Concurrent Computer Corporation
Concurrent_Computer_Corporation
Variable used in a concurrent system
preemption or disabling hardware interrupts. This approach does not work on multiprocessor systems where it is possible for two programs sharing a semaphore to
Semaphore_(programming)
Series of GPUs by Nvidia
January 9, 2025. "VESA to Update DisplayPort 2.1 with New Active Cable Specification for Up to 3x Longer DP80 Cables". VESA (Press release). January 6, 2025
GeForce_RTX_50_series
Commercial Linux distribution
chips as of 2024, it supports X86, ARM, SW64, RISC-V, and LoongArch multiprocessor architectures, and PowerPC. It supports chips such as HiSilicon Industrial
EulerOS
2001 family of microprocessors by IBM
microprocessor to do so. POWER4 Chip was first commercially available multiprocessor chip. The original POWER4 had a clock speed of 1.1 and 1.3 GHz, while
POWER4
add-on cards to the motherboard. MBus was first used in Sun's first multiprocessor SPARC-based system, the SPARCserver 600MP series (launched in 1991)
MBus_(SPARC)
General-purpose functional programming language
Peter; Nardelli, Francesco Zappa (2009). The Semantics of Power and ARM Multiprocessor Machine Code (PDF). DAMP 2009. pp. 13–24. doi:10.1145/1481839.1481842
Standard_ML
Retrieved 30 October 2014. Intel Xeon Processor C5500/C3500 series specification update (PDF)[permanent dead link] "Xeon L3403". Retrieved 30 October
List of Intel Xeon processors (Nehalem-based)
List_of_Intel_Xeon_processors_(Nehalem-based)
Graphics processing unit brand
multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output
Intel_Arc
Personal computer by Apple Computer
powerful Mac ever in Apple's four-digit model numbering system, the last multiprocessor Mac for three years, and the last model with six or more expansion slots
Power_Macintosh_9600
Lightweight threading implemented in userspace
on multiprocessors, An MT Java application could not harness true OS concurrency for faster applications on either uniprocessors or multiprocessors. To
Green_thread
In computing, an operation whereby a process creates a copy of itself
1960s as one of the earliest references to a fork concept appeared in A Multiprocessor System Design by Melvin Conway, published in 1962. Conway's paper motivated
Fork_(system_call)
Boot loader for Microsoft Windows
HAL set hardware interrupts to only the highest numbered processor on multiprocessor systems. /KERNEL=filename – Sets a different kernel image to use. /MAXMEM=nnn
NTLDR
Concurrent execution of multiple processes
more than one task to advance over a given period of time. Even on multiprocessor computers, multitasking allows many more tasks to be run than there
Computer_multitasking
Multi-core microprocessor microarchitecture
Processing Unit, an emerging class of processor with some similar features Multiprocessor system on a chip Cell software development Xenon (processor) PowerPC
Cell_(processor)
Supercomputer manufactured by Cray
The Cray XC30 is a massively parallel multiprocessor supercomputer manufactured by Cray. It consists of Intel Xeon processors, with optional Nvidia Tesla
Cray_XC30
Programming paradigm in which many processes are executed simultaneously
the 1970s, was among the first multiprocessors with more than a few processors. The first bus-connected multiprocessor with snooping caches was the Synapse
Parallel_computing
Computer bus standard physically based on Eurocard sizes
These architectures can be used as message switches, routers and small multiprocessor parallel architectures. VITA's application for recognition as an accredited
VMEbus
Unix System V framework
Specification, Version 3 from The Open Group. Presotto, David L. (1990). Multiprocessor streams for Plan 9. Proc. UKUUG Summer Conf. CiteSeerX 10.1.1.42.1172
STREAMS
Router architecture
Local and Metropolitan Area Networks (LANMAN), May 1998 Shared Memory Multiprocessor Architectures for Software IP Routers, Y. Luo et al., IEEE Transactions
Data_plane
2017 family of multi-core microprocessors by IBM
as CAPI 2.0 and CAPI 1.0 devices designed for POWER8. Multiprocessor (symmetric multiprocessor system) links to connect other POWER9 processors on the
POWER9
Open standard for parallelizing
conditions. As of 2017[update] only runs efficiently in shared-memory multiprocessor platforms (see however Intel's Cluster OpenMP Archived 2018-11-16 at
OpenMP
Series of microprocessors from IBM
update, fabricated on the same process as POWER6. The POWER7 symmetric multiprocessor design was a substantial evolution from the POWER6 design, focusing
IBM_Power_microprocessors
GPU microarchitecture by Nvidia
9 MTr/mm2 ? Graphics processing clusters 8 7 6 6 3 2 2 1 Streaming multiprocessors 128 84 60 48 30 20 16 12 CUDA cores 8192 10752 7680 6144 3840 2560
Ampere_(microarchitecture)
coherency The process of keeping data in multiple caches synchronised in a multiprocessor shared memory system, also required when DMA modifies the underlying
Glossary of computer hardware terms
Glossary_of_computer_hardware_terms
In computing, a lock which causes a thread to loop continuously
for Shared-Memory Multiprocessors" by Thomas E. Anderson Paper "Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors" by John M. Mellor-Crummey
Spinlock
Family of personal computers
shared memory. The Hydra card provided arbitration logic to manage the multiprocessor functionality, avoiding the need for each processor card to have such
Risc_PC
Western Australia, 1991 T.H. MacKenzie, T.I. Dix, "A distributed memory multiprocessor implementation of C-with-Ease," IEEE International Conference on Parallel
Ease_(programming_language)
High-speed interconnect technology
Devices based on this specification saw commercial use in wireless baseband, imaging and military computing. The RapidIO specification revision 1.3 was released
RapidIO
Series of x86 manycore processors from Intel
x86 architecture based processor design, extended to a cache-coherent multiprocessor system connected via a ring bus to memory; each core was capable of
Xeon_Phi
Series of 16-bit minicomputers
of prototype 11/74s (of various types) were built and at least two multiprocessor systems were sent to customers for beta testing, but no systems were
PDP-11
Massachusetts computer pioneer
Performance Analysis". Workshop on Experiences with Distributed and Multiprocessor Systems. Usenix Association: 105–126. Retrieved 29 December 2023. Compro
Encore_Computer
GPU microarchitecture by Nvidia
individual triangles. Features in Turing: CUDA cores (SM, Streaming Multiprocessor) Compute Capability 7.5 traditional rasterized shaders and compute concurrent
Turing_(microarchitecture)
Microprocessor designed by the Moscow Center of SPARC Technologies
ready-made computing modules and machines takes at least 1 year, and multiprocessor systems and complex computing systems – at least 2 years. Elbrus-2S+
Elbrus_2000
Family of computers 1970–1990
memory operating systems (DOS/VS, OS/VS1, OS/VS2). A tightly coupled multiprocessor (MP) model was available, as was the ability to loosely couple this
IBM_System/370
Set of computers configured in a distributed computing system
storage subsystem in order to distribute the workload. Unlike standard multiprocessor systems, each computer could be restarted without disrupting overall
Computer_cluster
Design principle in computer science
Levin; C. Pierson; F. Pollack (June 1974). "HYDRA: the kernel of a multiprocessor operating system". Communications of the ACM. 17 (6): 337–345. doi:10
Separation of mechanism and policy
Separation_of_mechanism_and_policy
Software framework for audio
synthesis. Hardware mixing of multiple channels. Full-duplex operation. Multiprocessor-friendly, thread-safe device drivers. Besides the sound device drivers
Advanced Linux Sound Architecture
Advanced_Linux_Sound_Architecture
Consistency model in concurrent computing
usually in what is referred to as "program order". Program order in a multiprocessor system is the execution of instructions resulting in the same outcome
Processor_consistency
are intended to execute efficiently on single-processor machines, multiprocessors with shared memory or distributed multicomputers. PCN was developed
Program_Composition_Notation
Series of GPUs by Nvidia
bit on GK106, further saving power. Nvidia also changed the streaming multiprocessor design from that of Kepler (SMX), naming it SMM. The layout of SMM units
GeForce_800M_series
Creation and maintenance of software
enable a multi-threaded implementation that runs significantly faster on multiprocessor computers. During the analysis and design phases of software development
Software_development
Microprocessor developed by Sun Microsystems
cache tags is used by cache coherency traffic, which is required in the multiprocessor systems the UltraSPARC III is designed to be used in. As the maximum
UltraSPARC_III
MULTIPROCESSOR SPECIFICATION
MULTIPROCESSOR SPECIFICATION
MULTIPROCESSOR SPECIFICATION
MULTIPROCESSOR SPECIFICATION
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English
Variant spelling of English Janine, JANNINE means "God is gracious."
MULTIPROCESSOR SPECIFICATION
MULTIPROCESSOR SPECIFICATION
MULTIPROCESSOR SPECIFICATION
MULTIPROCESSOR SPECIFICATION
MULTIPROCESSOR SPECIFICATION
n.
The designation of particulars; particular mention; as, the specification of a charge against an officer.
a.
Admitting specification; capable of being specified.
v. t.
An accusation of a wrong of offense; allegation; indictment; specification of something alleged.
n.
The act of specifying or determining by a mark or limit; notation of limits.
n.
A written statement containing a minute description or enumeration of particulars, as of charges against a public officer, the terms of a contract, the description of an invention, as in a patent; also, a single article, item, or particular, an allegation of a specific act, as in a charge of official misconduct.