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Iddq testing

Iddq testing is a method for testing CMOS integrated circuits for the presence of manufacturing faults. It relies on measuring the supply current (Idd)

Power gating

reducing stand-by or leakage power, power gating has the benefit of enabling Iddq testing. Power gating affects design architecture more than clock gating

Logic redundancy

methods (single stuck-at fault models). Testing might be possible using IDDQ models. Logic redundancy is, in general, not desired. Redundancy, by definition

PA-7100LC

D. (1997). "IDDQ testing of a 180 MHz HP PA-RISC microprocessor with redundancy programmed caches". IEEE International Workshop on IDDQ Digest of Technical

Design for testing

design for debug or design for debuggability. BIST Design for X Fault grading Iddq testing JTAG Ben-Gal I., Herer Y. and Raz T. (2003). "Self-correcting inspection

Leakage (electronics)

defects exhibit themselves as increased leakage. Thus measuring leakage, or Iddq testing, is a quick, inexpensive method for finding defective chips. Increased

Scan chain

design automation Integrated circuit design Serial Peripheral Interface Bus Iddq testing An example of a scan chain for stuck-at faults Boundary-Scan Chain

Stuck-at fault

sometimes called "windfall" fault coverage. Another type of testing called IDDQ testing measures the way the power supply current of a CMOS integrated circuit

Power optimization (EDA)

Multi-Threshold CMOS reduces stand-by or leakage power, and also enables Iddq testing. Long-Channel transistors: Transistors of more than minimum length